Design Engineer Jobs

About The Position

Requirements

• BS or MS in Electrical Engineering, Computer Engineering, or a related field, with 4+ years of relevant experience.
• Significant experience in custom IC design, mixed-signal design, standard-cell characterization, or digital timing methodology.
• Hands-on experience with transistor-level simulation using SPICE-class tools.
• Strong understanding of CMOS digital circuit design, including inverters, combinational logic, latches, flip-flops, transmission gates, clocked logic, and reset/set structures.
• Strong understanding of setup time, hold time, clock-to-Q delay, propagation delay, slew/load dependence, recovery/removal timing, and minimum pulse-width checks.
• Experience generating or validating Liberty .lib files.
• Experience with PVT-based characterization and corner analysis.
• Ability to analyze SPICE waveforms and debug unexpected circuit behavior.
• Scripting experience in Python, Tcl, Perl, shell, SKILL, or similar.
• Ability to work effectively with analog, digital, verification, STA, and physical design teams.
• Strong communication skills.

Nice To Haves

• Experience with Cadence Virtuoso, ADE Explorer/Assembler, Spectre, and related analog/mixed-signal design tools.
• Experience with library characterization tools such as Cadence Liberate, Synopsys SiliconSmart, Solido Characterization Suite, or custom in-house characterization flows.
• Experience with STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Experience with extracted-netlist simulation using DSPF, SPEF, or post-layout parasitic views.
• Experience with level shifters, synchronizers, comparators, custom clocking circuits, and clock-domain-crossing interfaces.
• Experience modeling circuits with analog-dependent timing behavior, metastability, hysteresis, or threshold-crossing behavior.
• Experience in advanced CMOS technology nodes.
• Familiarity with reliability and robustness analysis, including aging, EM/IR, supply noise, mismatch, Monte Carlo analysis, and local variation.
• Experience creating Verilog, Verilog-A, SystemVerilog, or specify-block models to accompany Liberty timing models.
• Familiarity with digital implementation flows including synthesis, place-and-route, timing closure, and signoff.

Responsibilities

• Generate and maintain Liberty .lib models for custom digital and analog-digital interface circuits.
• Define and characterize applicable timing arcs, including input-to-output delay, clock-to-Q, setup and hold, recovery and removal, minimum pulse width, enable/disable, and tristate or conditional timing.
• Characterize timing across relevant PVT corners, input slew and output load ranges, and extracted parasitic conditions.
• Model pin capacitance, transition behavior, leakage, dynamic power, and other Liberty attributes as needed.
• Validate generated Liberty files against transistor-level simulation results and downstream STA behavior, and ensure compatibility with digital implementation and signoff tools.
• Build, debug, and maintain transistor-level simulation testbenches for custom interface circuits; run SPICE or FastSPICE simulations.
• Develop measurement methodologies for timing constraints and delays, transition time, minimum pulse width, recovery/removal, and metastability-sensitive behavior.
• Perform simulations across PVT and parasitic-extracted views; analyze waveforms and investigate timing anomalies, non-monotonicity, race conditions, glitches, contention, or metastable behavior.
• Create automated characterization flows using scripting languages such as Python, Tcl, Perl, shell, or SKILL.
• Collaborate with digital design, STA, verification, physical design, and analog/mixed-signal teams to integrate custom Liberty models into synthesis, place-and-route, timing signoff, and verification flows.
• Review STA results and work with layout and physical design teams to ensure timing and parasitic impacts are represented appropriately.
• Document characterization methods, simulation conditions, measurement definitions, and modeling assumptions; produce characterization reports and validation summaries.
• Define standard practices and create reusable characterization templates, testbenches, and automation infrastructure.
• Mentor junior engineers in custom timing characterization, Liberty modeling, and SPICE-based validation.

Benefits

• Medical, dental, and vision insurance.
• Basic and supplemental life insurance.
• Paid parental leave.
• Short- and long-term disability.
• 401(k) with company match of up to 5%.
• Education Support Program.
• Stock options for regular employees working at least 20 hours per week.
• Paid time off of up to four weeks per year based on weekly scheduled hours.
• Up to 14 company-paid holidays.
• Depending on role type and job level, potential eligibility for benefits and bonuses based on individual contributions and company results.