Senior Principal / Distinguished Engineer – SerDes Analog/Mixed-Signal Design

Upscale, Inc. • Headquarters, KY

13d • $261,000 - $297,000

About The Position

Upscale AI is developing next-generation SerDes technology to provide the bandwidth, power efficiency, and scalability needed by future AI infrastructure. The Senior Principal / Distinguished Engineer will lead technically challenging design efforts, influence circuit and subsystem architecture, and make critical design decisions across engineering disciplines. The role requires deep circuit expertise, sound engineering judgment, and a system-level perspective to deliver differentiated high-speed silicon solutions.

Requirements

• M.S. or Ph.D. in Electrical Engineering or a related field.
• Extensive experience in analog/mixed-signal IC design, 100G+ high-speed circuit design, or advanced semiconductor product development.
• Demonstrated record of delivering complex circuit designs from architecture through implementation and silicon validation.
• Strong debugging skills and ability to solve ambiguous, cross-disciplinary technical problems.
• Excellent technical communication skills and ability to influence engineering decisions across teams.

Nice To Haves

• Significant experience developing 100G+ high-speed SerDes or other high-performance analog/mixed-signal IP.
• Expertise in advanced CMOS process technologies and related circuit-design, physical-implementation, and variability challenges.
• Expertise in one or more of: Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD); phase interpolator, injection-locked oscillator, multi-phase clock generator; high-speed time-interleaved DAC and line driver; transimpedance amplifier, CTLE, PGA, Cherry-Hooper amplifier, high-speed voltage followers; time-interleaved SAR ADC, track-and-hold circuits; bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, or R2R DAC.
• Demonstrated success driving critical circuit blocks or subsystems to silicon with strong performance and quality.
• Experience influencing architecture and design methodology beyond an individual circuit block.
• Experience with circuit modeling, simulation automation, optimization, and silicon-to-model correlation.
• Patents, technical publications, or other evidence of meaningful technical innovation.

Responsibilities

• Lead the design and implementation of complex high-speed analog/mixed-signal circuits and critical SerDes IP.
• Define circuit approaches and design methodologies to meet aggressive performance, power, area, and robustness objectives for 100G+ SerDes PHYs.
• Resolve challenging circuit-design issues through first-principles analysis, modeling, simulation, and silicon-based investigation.
• Lead technical reviews and influence decisions across architecture, analog/mixed-signal design, digital design, layout, physical design, and validation.
• Drive design closure for complex implementations, including post-layout verification, performance optimization, and silicon correlation.
• Identify opportunities for architectural innovation, design automation, and improved engineering efficiency.
• Contribute to technical roadmaps, project planning, and risk mitigation for next-generation SerDes products.
• Promote rigorous engineering practices, design quality, and knowledge sharing across the organization.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Ph.D. or professional degree