Senior / Staff Engineer – SerDes Analog/Mixed-Signal Design
About The Position
Upscale AI is developing next-generation high-speed connectivity solutions for AI infrastructure and data centers. The Senior / Staff Engineer will develop advanced SerDes circuits and foundational IP for next-generation high-bandwidth, energy-efficient interconnects. The role involves analog and mixed-signal circuit design, simulation, and optimization, with collaboration across architecture, digital design, physical design, layout, and validation teams. The engineer will contribute to design integration and closure, support physical implementation and silicon characterization, and improve design productivity through scripting and automation. Upscale, Inc. builds high-performance infrastructure for demanding AI workloads and emphasizes ownership, technical rigor, and speed. Compensation is $223,000–$243,000 per year, with placement in the range depending on experience, skills, and impact.
Requirements
- B.S., M.S., or Ph.D. in Electrical Engineering or a related technical field.
- Relevant experience in analog/mixed-signal IC design, high-speed circuit design, or semiconductor product development.
- Solid understanding of transistor-level circuit design, circuit analysis, and analog/mixed-signal simulation.
- Hands-on experience with SPICE-based simulators and standard IC design workflows.
- Familiarity with scripting languages such as Python, MATLAB, or equivalent tools.
- Strong analytical, problem-solving, communication, and teamwork skills.
Nice To Haves
- Experience developing high-speed SerDes, wireline transceivers, data converters, clocking circuits, or other analog/mixed-signal IP.
- Experience developing AI-driven schematic or layout workflows.
- Familiarity with advanced CMOS process technologies and their circuit-design challenges.
- Experience with post-layout simulation, parasitic extraction, and circuit-performance optimization.
- Exposure to silicon bring-up, characterization, and circuit debug.
- Ability to independently own design tasks and drive them to completion.
- Experience with one or more of the following: Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD); phase interpolator, injection-locked oscillator, multi-phase clock generator; high-speed time-interleaved DAC and line driver; transimpedance amplifier, CTLE, PGA, high-speed voltage followers; time-interleaved SAR ADC, track-and-hold circuits; bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, or R2R DAC.
Responsibilities
- Design, simulate, and optimize analog and mixed-signal circuits for next-generation high-speed SerDes and related IP.
- Perform transistor-level circuit design, behavioral modeling, and performance analysis to meet power, performance, and area targets.
- Develop simulation testbenches, analyze circuit behavior, and troubleshoot performance or convergence issues.
- Collaborate with architecture, digital design, physical design, layout, and validation teams to drive design integration and closure.
- Participate in design reviews, identify potential risks, and develop practical solutions to circuit-level problems.
- Support physical implementation, post-layout verification, silicon characterization, and debug as needed.
- Develop scripts and automation to improve simulation efficiency, design productivity, and data analysis.
- Document design methodologies, simulation results, and technical findings.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
