Senior Physical Design Engineer
About The Position
Broadcom’s ASIC Products Division (APD) develops custom high-performance silicon solutions for hyperscale cloud providers, AI companies, and networking infrastructure leaders. The Physical Design team implements complex ASIC architectures using advanced physical design methodologies, advanced process nodes, and 2.5D/3D chiplet integration. The Senior Physical Design Engineer will work on next-generation AI and PCIe Switch products, applying in-depth physical design expertise to take designs from RTL through silicon tape-out. The role leads block-level and top-level implementation, advanced-node execution, and timing and power closure.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- At least 8 years of hands-on physical design experience, including successful tape-outs of complex, high-frequency, ultra-large-scale networking or AI ASICs.
- Direct tape-out experience in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency with physical design tools: Cadence Innovus for place and route; Synopsys PrimeTime or Cadence Tempus for timing and STA; StarRC or QRC for extraction; RedHawk for IR/EM; and Siemens Calibre for DRC/LVS.
- Advanced TCL, Python, and Unix shell scripting skills for flow automation and database manipulation.
- Excellent technical leadership, problem-solving, and cross-functional communication skills.
Nice To Haves
- Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power CTS.
- Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock/power gating.
Responsibilities
- Lead block-level and top-level implementation from floorplanning through GDSII stream-out using Cadence Innovus.
- Execute floorplanning, placement, clock tree synthesis (CTS), routing, and timing and power optimization on advanced technology nodes, including 5nm, 3nm, and 2nm.
- Perform multi-corner, multi-mode (MCMM) static timing analysis, signal-integrity optimization, and power-grid signoff optimization, including static and dynamic IR-drop and electromigration (EM), using PrimeTime, Voltus, or RedHawk.
Benefits
- Discretionary annual bonus.
- Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
- Medical, dental, and vision plans.
- 401(k) participation with company matching.
- Employee Stock Purchase Program (ESPP).
- Employee Assistance Program (EAP).
- Company-paid holidays, paid sick leave, and vacation time.
- Paid family leave and other leaves of absence in accordance with applicable laws.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
