Senior Physical Design Engineer
About The Position
Broadcom’s ASIC Products Division (APD) is seeking a Senior Physical Design Engineer to work on next-generation Artificial Intelligence and PCIe Switch products. The Physical Design team implements complex custom ASICs for cloud, AI, and networking applications, using advanced physical design methodologies and chiplet integration. The role requires in-depth expertise across the physical design process from RTL through silicon tape-out. The engineer will lead block-level and top-level implementation through GDSII stream-out, and drive physical design and signoff activities on advanced technology nodes. The work includes floorplanning, placement, clock-tree synthesis, routing, timing and power optimization, static timing analysis, signal-integrity optimization, and power-grid signoff.
Requirements
- B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
- At least 8 years of hands-on physical design experience with successful tape-outs of complex, high-frequency, ultra-large-scale networking or AI ASICs.
- Direct experience executing tape-outs in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
- High proficiency with physical design and implementation flows, including Cadence Innovus for place and route.
- Proficiency with Synopsys PrimeTime or Cadence Tempus for timing and static timing analysis.
- Experience with StarRC or QRC for extraction, and RedHawk for IR/EM analysis.
- Experience with Siemens Calibre for DRC/LVS.
- Advanced TCL, Python, and Unix shell scripting skills for flow automation and database manipulation.
- Excellent technical leadership, problem-solving, and cross-functional communication skills.
Nice To Haves
- Strong background in high-speed clock network implementation, including H-tree, mesh, and low-power CTS.
- Experience with power-aware implementation flows, including UPF/CPF, multi-voltage domains, and clock/power gating.
Responsibilities
- Lead block-level and top-level implementation from floorplanning through GDSII stream-out using Cadence Innovus.
- Drive floorplanning, placement, clock-tree synthesis, routing, and timing and power optimization on advanced technology nodes.
- Perform multi-corner multi-mode static timing analysis and signal-integrity optimization.
- Optimize power grids and perform static and dynamic IR-drop and electromigration signoff.
- Automate physical design flows and manipulate design databases using scripting.
Benefits
- Discretionary annual bonus
- Competitive new-hire equity grant and annual equity awards
- Medical insurance
- Dental insurance
- Vision insurance
- 401(k) participation with company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company-paid holidays
- Paid sick leave
- Vacation time
- Paid family leave and other leaves of absence in accordance with applicable laws
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What This Job Offers
Job Type
Full-time
Career Level
Senior
