Physical Design Engineer

Broadcom • Fort Collins, CO

6d • $143,800 - $230,000

About The Position

The Physical Design Engineer works on ASIC and SoC design implementation, with a focus on place and route and/or timing closure. The role covers implementation activities at both block and SoC level, including floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification such as LVS/DRC. The engineer drives tools and methodologies to achieve PPA metrics, performs equivalence checks and power optimization, implements timing and functional ECOs, and applies Broadcom’s design methodology and milestone flow to meet its criteria for right-first-time silicon.

The position calls for hands-on experience with timing analysis and place-and-route tools, along with the ability to solve problems, work independently, contribute in a global and dynamic team, adapt to new tools and methodologies, and communicate effectively. A BS in Electrical Engineering, Computer Engineering, or a related field with 12+ years of related experience, or an MS in a related field with 10+ years of related experience, is required.

The stated annual base salary range is USD 143,800 to USD 230,000. Compensation also includes eligibility for a discretionary annual bonus and the opportunity for new-hire and annual equity awards, subject to relevant plans and agreements. Broadcom offers medical, dental, and vision plans; 401(k) participation with company matching; an Employee Stock Purchase Program; an Employee Assistance Program; company-paid holidays; paid sick leave and vacation; and leaves of absence, including Paid Family Leave in accordance with applicable law.

Requirements

• Primary expertise in place and route and/or timing, including constraints and STA.
• Proficiency in design implementation activities at both block and SoC level.
• Experience in floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification and/or constraints development, constraints validation, timing analysis, and closure.
• Experience with formal verification, timing analysis, and ECO implementation.
• Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
• Good problem-solving skills.
• Ability to work independently as a self-starter.
• Experience working in a global team and dynamic environment.
• Ability to learn and adapt to new tools and methodologies quickly.
• Excellent communication skills.
• BS in Electrical Engineering, Computer Engineering, or a related field and 12+ years of related experience; or MS in Electrical Engineering, Computer Engineering, or a related field and 10+ years of related experience.

Nice To Haves

• Experience with tools such as PrimeTime, ICC2, Innovus, Caliber, and LEC is highly desirable.
• Full-chip tapeout experience based on 7nm and lower technologies is highly preferred.

Responsibilities

• Perform design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC).
• Drive tools and methodologies to achieve desired PPA metrics.
• Complete equivalence checks, static timing analysis (STA), timing closure, and power optimization.
• Implement timing and functional engineering change orders (ECOs).
• Apply Broadcom’s design methodology and milestone flow to meet its criteria for right-first-time silicon.

Benefits

• Discretionary annual bonus eligibility.
• Opportunity to receive a competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior