Physical Design Engineer

Broadcom • San Jose, CA

5d

About The Position

Broadcom’s ASIC Products Division (APD) is seeking a motivated new college graduate to join its Physical Design team. The team develops custom, high-performance silicon solutions for technology companies in cloud computing, AI, and networking. It works on advanced physical design methodologies, leading-edge process nodes, and 2.5D/3D chiplet integration.

The engineer will work alongside experienced colleagues to execute implementation tasks for next-generation networking, AI/ML accelerator, and custom cloud ASICs. The role provides hands-on experience in block-level floorplanning, synthesis, place and route, clock tree synthesis, timing closure, and signoff across advanced process nodes. The position is based in San Jose, California, and is full-time.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering and 2 years of experience, or a master’s degree in Electrical Engineering or Computer Engineering; for the master’s degree pathway, graduation must have been within the past 12 months.
• Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
• Familiarity with static timing analysis concepts, clocking, and setup/hold timing.
• Hands-on coursework, lab experience, or academic projects using EDA design tools such as Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools.
• Proficiency in scripting languages such as TCL, Python, Ruby, or Bash.
• Legal authorization to work in the United States.

Nice To Haves

• Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
• Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
• Excellent problem-solving, debugging, and analytical skills.

Responsibilities

• Participate in block-level floorplanning and run placement and route (P&R) flows using industry-standard EDA tools.
• Perform static timing analysis (STA), debug timing paths, and execute engineering change orders (ECOs) for timing closure.
• Run physical verification checks, including DRC, LVS, ERC, and antenna checks, and resolve signoff violations.
• Analyze IR drop and electromigration (EM) to ensure power grid integrity.
• Develop and maintain automated scripts using TCL, Python, Ruby, or other listed scripting languages to improve flow efficiency and productivity.

Benefits

• Discretionary annual bonus eligibility.
• Opportunity to receive a competitive new-hire equity grant and annual equity awards, subject to relevant plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level