Physical Design Engineer

Broadcom • San Jose, CA

6d • $82,500 - $132,000

About The Position

Broadcom’s ASIC Products Division (APD) is seeking a motivated new college graduate to join its Physical Design team. The team partners with technology companies to design and manufacture custom high-performance ASICs for cloud, AI/ML, and networking applications. Its work includes advanced physical design methodologies, leading-edge process nodes, and 2.5D/3D chiplet integration.

The engineer will work alongside experienced colleagues to execute implementation tasks for next-generation ASICs and gain hands-on experience in block-level floorplanning, synthesis, place and route (P&R), clock tree synthesis (CTS), timing closure, and signoff across N5, N3, N2, and A14 nodes.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2 years of experience, or a Master’s degree in Electrical Engineering or Computer Engineering with graduation within the past 12 months.
• Solid understanding of digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
• Familiarity with static timing analysis concepts, clocking, and setup/hold timing.
• Hands-on coursework, lab experience, or academic projects using EDA design tools such as Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools.
• Proficiency in scripting languages such as TCL, Python, Ruby, or Bash.
• Legal authorization to work in the U.S.

Nice To Haves

• Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
• Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
• Excellent problem-solving, debugging, and analytical skills.

Responsibilities

• Participate in block-level floorplanning and run placement and route (P&R) flows using industry-standard EDA tools.
• Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
• Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations.
• Analyze IR drop and electromigration (EM) to ensure power grid integrity.
• Develop and maintain automated scripts using TCL, Python, or Ruby to improve flow efficiency and productivity.

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and opportunity for annual equity awards
• Medical, dental, and vision plans
• 401(K) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level