Physical Design Engineer
About The Position
Qualcomm Technologies, Inc. is seeking Physical Design Engineers for its growing SoC and ASIC Design organization. Engineers may contribute to projects in areas including high-performance computing, AI, mobile, automotive, data centers, and next-generation semiconductor technologies. The role covers aspects of ASIC and SoC physical design, including floorplanning, clock tree synthesis, low-power implementation, timing analysis, design methodology, automation, and enabling new technology nodes. The team develops leading-edge products on advanced process technologies and collaborates across design, verification, implementation, and physical design teams. The engineer will drive the physical design flow from synthesized netlist through tape-out, develop implementation solutions for complex, high-speed, low-power ASICs and SoCs, and support design convergence through sign-off. The position also involves developing low-power methodologies, customized place-and-route solutions, and automation and productivity tools.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; the minimum qualifications also specify a bachelor's degree in Science, Engineering, or a related field.
- 2–10+ years of industry experience or relevant academic/project experience in Physical Design.
- Perl/Tcl and Python skills are needed.
- Strong problem-solving and ASIC development/debugging skills.
Nice To Haves
- Experience in ASIC/SoC physical design implementation.
- Experience with place and route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Experience with static timing analysis and timing closure using Synopsys PrimeTime SI.
- Experience with physical verification and design sign-off methodologies.
- Experience with formal verification techniques and tools.
- Experience with power-domain implementation and low-power design methodologies.
- Experience with clock tree synthesis (CTS), routing, and timing optimization.
- Experience with low-power implementation techniques.
- Experience with signal integrity, noise analysis, and MMMC sign-off flows.
- Experience with DFT-aware physical implementation and constraint management.
- Programming and automation experience using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Responsibilities
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis, routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
- Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
- Competitive benefits package designed to support employees at work, at home, and at play.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
