Physical Design Engineer
About The Position
Qualcomm is seeking Physical Design Engineers to join its SoC and ASIC Design organization. Engineers may contribute to projects involving high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. The role covers aspects of ASIC and SoC physical design, including floorplanning, clock tree synthesis, low-power implementation, timing analysis, design methodology, automation, and enabling new technology nodes. The position offers the opportunity to work with advanced process technologies and collaborate with design, verification, implementation, and physical design teams.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2–10+ years of industry experience or relevant academic/project experience in Physical Design.
- Minimum qualifications: Bachelor's degree in Science, Engineering, or a related field and 4+ years of ASIC design, verification, validation, integration, or related work experience; or a Master's degree in those fields and 3+ years of relevant work experience; or a PhD in those fields and 2+ years of relevant work experience.
- Perl/Tcl and Python skills are needed.
- Strong problem-solving and ASIC development/debugging skills.
Nice To Haves
- Experience in ASIC/SoC physical design implementation.
- Place-and-route experience using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static timing analysis and timing closure experience using Synopsys PrimeTime SI.
- Experience with physical verification and design sign-off methodologies.
- Experience with formal verification techniques and tools.
- Experience with power-domain implementation and low-power design methodologies.
- Experience in clock tree synthesis (CTS), routing, and timing optimization.
- Experience with low-power implementation techniques.
- Experience with signal integrity, noise analysis, and MMMC sign-off flows.
- Experience with DFT-aware physical implementation and constraint management.
- Programming and automation experience using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Responsibilities
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis, routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
- Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants, except for employees on sales-incentive plans.
- Competitive benefits package designed to support employees at work, at home, and at play.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
