Sr Physical Design Engineer

Advanced Micro Devices, Inc • Santa Clara, CA

5d

About The Position

Join AMD’s team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this physical design engineering role, you will contribute across the full RTL-to-GDS implementation lifecycle on challenging designs where timing, power, area, and physical quality are critical.

You will collaborate with geographically distributed engineering teams and work across synthesis, floorplanning, timing-driven place and route, clock tree synthesis, physical verification, and final signoff. The role also offers the opportunity to influence design methodologies and automated flows used to deliver complex IP efficiently and with high quality. The successful candidate is collaborative and technically curious, communicates clearly across disciplines and locations, prioritizes work across multiple projects, and applies analytical problem-solving while balancing design targets and schedules. The role is not eligible for visa sponsorship.

Requirements

• Experience taking digital designs through the RTL-to-GDS physical design flow.
• Experience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.
• Experience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.
• Knowledge of timing, power, and area optimization techniques.
• Understanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.
• Experience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.
• Experience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.
• Bachelor’s or master’s degree in electrical engineering, computer science, or a related technical discipline is preferred; relevant technical education or equivalent practical experience in semiconductor or physical design engineering is valued.

Nice To Haves

• Experience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.
• Verilog experience.
• Familiarity with schematic, layout, circuit simulation, or logic simulation tools.
• Experience developing, automating, or improving physical design methodologies and flows.
• Academic or professional exposure to high-speed SerDes PHY, high-performance digital IP, or related semiconductor design.

Responsibilities

• Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
• Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.
• Analyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.
• Support floorplanning, design methodology development, and integration of complex IP.
• Perform and support logic equivalence, timing, physical, and electrical quality checks.
• Troubleshoot implementation and timing challenges and collaborate with design teams to drive issues to closure.
• Identify opportunities to improve automation, design methodology, quality, and overall design cycle time.
• Support final signoff and delivery of large, high-performance IP blocks.
• Build familiarity with the team’s design environment and methodologies, progressing toward independent ownership of physical design blocks and optimization activities.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior