Physical Design Engineer

Qualcomm • San Diego, CA

1d • $174,400 - $261,600

About The Position

Qualcomm Technologies, Inc. is seeking Physical Design Engineers to join its SoC and ASIC Design organization. The role may contribute to projects in high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers may work on floorplanning, clock tree synthesis, low-power implementation, timing analysis, design methodology, automation, and enabling new technology nodes. The position involves developing leading-edge products on advanced process technologies and collaborating with design, verification, implementation, and physical design teams.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of industry experience or relevant academic/project experience in Physical Design.
• Alternatively, a bachelor's degree in Science, Engineering, or a related field and 6+ years of ASIC design, verification, validation, integration, or related work experience; a master's degree and 5+ years; or a PhD and 4+ years.
• Perl/Tcl and Python skills are needed.
• Strong problem-solving and ASIC development/debugging skills.

Nice To Haves

• Experience in ASIC/SoC Physical Design implementation.
• Experience with place and route using Cadence Innovus and/or Synopsys Fusion Compiler.
• Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
• Experience with physical verification and design sign-off methodologies.
• Experience with formal verification techniques and tools.
• Experience with power domain implementation and low-power design methodologies.
• Experience with clock tree synthesis (CTS), routing, and timing optimization.
• Experience with low-power implementation techniques.
• Experience with signal integrity, noise analysis, and MMMC sign-off flows.
• Experience with DFT-aware physical implementation and constraint management.
• Programming and automation experience using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.

Responsibilities

• Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
• Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
• Perform floorplanning, partitioning, power planning, and IR-drop analysis.
• Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
• Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
• Perform RC extraction, physical verification, and formal verification activities.
• Implement engineering change orders (ECOs) and support design convergence through sign-off.
• Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
• Contribute to innovative low-power implementation methodologies and customized place-and-route solutions.
• Develop automation and productivity tools using scripting languages and software development techniques.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
• Competitive benefits package designed to support success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior