Physical Design Engineer

Apple • Cupertino, CA

4d • $174,149 - $225,300

About The Position

Apple Inc. is hiring a Physical Design Engineer to work in Cupertino, California, and various unanticipated locations throughout the USA. The role analyzes and performs static and dynamic power reduction for advanced-node technology and complex SoC designs, implements low-power design techniques, and meets power target goals.

The engineer performs critical Engineering Change Orders (ECOs) to fix violations identified across timing, physical verification, power-grid integrity, and logic-equivalence checks, supporting design closure for tape-out. The role also develops CAD-tool scripts and programming for automation, problem solving, and efficiency improvement. It includes chip or partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve design power, performance, and area.

The engineer works with the logic design team to understand partition architecture and address physical design aspects early in the design cycle. They complete netlist-to-GDS2 implementation for partitions, meeting schedule and design goals, and conduct timing, physical, and electrical verification while driving signoff closure. The role also resolves design and flow issues related to physical design, identifies potential solutions, and drives their execution. The position is 40 hours per week.

Requirements

• Master's degree or foreign equivalent in Computer Engineering or a related field.
• Three years of experience in the job offered or a related occupation.
• Experience using Innovus or Fusion Compiler APR tools for implementation design, including physical-design workflows and implementation tasks.
• Experience tuning implementation design flows and methodologies to improve power, performance, and area.
• Experience performing static timing analysis and timing convergence, conducting IR/IVD analysis, implementing violation fixes, and debugging and resolving LVC/DRC violations.
• Experience with physical design on advanced technology nodes (7nm and below), and knowledge of modern CMOS technology and fabrication fundamentals.
• Experience in block-level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO implementation.
• Experience with low-power design techniques, including clock gating, power gating, and multi-voltage-domain design.
• Experience using scripting languages such as TCL, Perl, or Python to implement automation techniques.
• Experience applying top-down and bottom-up design approaches and resolving interblock timing and PDV-related issues.

Responsibilities

• Analyze and perform static and dynamic power reduction for advanced-node technology and complex SoC designs.
• Implement low-power design techniques and meet power target goals.
• Perform critical ECOs to fix violations identified through timing, physical verification, power-grid integrity, and logic-equivalence checks for design closure and tape-out.
• Develop scripts and programs for CAD-tool flow automation, problem solving, and efficiency improvement.
• Execute chip or partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve power, performance, and area.
• Work with the logic design team to understand partition architecture and address physical design aspects early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Perform timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve physical-design-related design and flow issues, identify potential solutions, and drive execution.

Benefits

• Opportunity to participate in discretionary employee stock programs, including discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level