Engineer II - Physical Design

Microchip Technology Inc. • Chandler, AZ

1d

About The Position

Join Microchip Technology Inc.’s Physical Design team to support semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, documentation, and tapeout-readiness activities. The role is suited to candidates with 2.5–5 years of relevant experience in ASIC or SoC physical design or a closely related area.

The Engineer independently executes defined physical-design assignments and coordinates assigned deliverables while collaborating with architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, manufacturing, and leadership teams. The role contributes to performance, power, area, physical-verification closure, reliability, and tapeout readiness.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field, with 2.5–5 years of relevant experience; closely related equivalent experience is also accepted.
• Relevant experience in ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, physical verification, EDA flows, or a closely related area.
• Demonstrated analytical thinking, semiconductor physical-design judgment, and structured problem solving.
• Demonstrated timing and power analysis, debugging, and root-cause analysis skills.
• Ability to produce technical documentation and communicate based on evidence.
• Cross-functional collaboration and a quality-focused approach.
• Ability to work with complex architecture, RTL, constraints, libraries, layout, timing, power, physical-verification, reliability, and manufacturing information.
• Demonstrated employment stability, reliability, and sustained accountability in prior roles.
• Integrity and accuracy in representing qualifications, experience, and credentials.

Nice To Haves

• Experience with ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, or physical verification.
• Experience with EDA tools, scripting, automation, design constraints, low-power implementation, variation analysis, design-for-test, advanced process nodes, or tapeout flows.
• Experience resolving timing, congestion, power, signal-integrity, physical-verification, integration, reliability, or manufacturability issues.
• Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.

Responsibilities

• Develop and maintain defined ASIC or SoC physical-design blocks, constraints, scripts, flows, and design data.
• Translate approved architecture and RTL requirements into synthesis, floorplan, placement, clock, routing, timing, power, and verification objectives.
• Execute implementation, regression, extraction, timing, power, physical-verification, and applicable signoff checks.
• Troubleshoot flow, constraint, timing, congestion, power, signal-integrity, physical-verification, and integration issues.
• Analyze reports, logs, results, defects, risks, dependencies, and technical tradeoffs; recommend actions.
• Maintain design configuration, scripts, run records, waiver evidence, release data, traceability, and technical documentation.
• Coordinate assigned deliverables across architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams.
• Support automation, reuse, corrective action, and continuous improvement.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level