The Senior Physical Design Engineer will drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals. The role includes floor planning complex ASIC/SoC designs, supporting timing closure, analyzing netlists, and collaborating across architecture, RTL, verification, and physical design teams to achieve design convergence. The engineer will also participate in design reviews and contribute to process and methodology improvements.
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Job Type
Full-time
Career Level
Senior