Design Engineer Jobs

About The Position

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field.
• Two years of experience in the job offered or a related occupation.
• Experience or education using PNR tools such as ICC, ICC2, or Innovus for SoC partition place and route, including floor planning, placement, clock optimization, routing, and timing and power optimization.
• Experience or education using timing-analysis tools such as Synopsys PrimeTime for timing analysis and timing ECO generation for SoC partition closure.
• Experience or education using TCL, Perl, or Python and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts for partition closure.
• Understanding of physical-design construction and analysis flows and methodologies sufficient to execute, close, and sign off SoC partitions.
• Understanding of transistors and digital circuits to meet requirements and make implementation, closure, and signoff trade-offs.
• Ability to interpret EMIR analysis results from tools such as Voltus or Redhawk and generate fixes for violations or QoR improvement.
• Ability to interpret physical-verification results from tools such as Calibre and generate fixes for violations.
• Ability to interpret LEC and low-power verification results from tools such as Conformal, Formality, VCLP, and CLP, and make fixes to address violations.

Responsibilities

• Work with logic design teams to understand partition architecture and drive physical design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedules and design goals.
• Own timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve physical-design and flow issues by identifying potential solutions and driving their execution.
• Coordinate place-and-route work among engineers; establish goals and milestones, plan short- and long-term work, and understand dependencies across top-level design, STA, and block place-and-route domains.
• Drive physical-design methodologies and best-known methods; develop guidelines and checklists, oversee execution, and track progress.
• Drive timing closure using physical synthesis and place-and-route tools, working with ASIC vendors.
• Drive frontend and backend implementation from RTL to GDS2, including synthesis, formal verification, floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Improve timing signoff criteria, timing-analysis methodologies, and flows, and develop or enhance ECO-generation scripts for timing closure.
• Perform floor planning, physical synthesis, and physical-design closure for large, complex designs with clock cycles at 1 GHz or higher.
• Drive physical-design and timing convergence for high-frequency, low-power designs at block, cluster, and/or full-chip level.
• Use PNR tools such as ICC, ICC2, or Innovus for place and route, including floor planning, placement, clock optimization, routing, and timing and power optimization.
• Use timing-analysis tools such as Synopsys PrimeTime for timing analysis and timing ECO generation.
• Use TCL, Perl, Python, and Unix scripting to summarize data, improve execution efficiency, and create custom scripts that support partition closure.
• Interpret EMIR analysis results from tools such as Voltus or Redhawk and generate fixes for violations or QoR improvement.
• Interpret physical-verification results from tools such as Calibre and generate fixes for violations.
• Interpret LEC and low-power verification results from tools such as Conformal, Formality, VCLP, and CLP, and make fixes to address violations.

Benefits

• Comprehensive medical coverage
• Dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple
• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards and discounted stock purchases through the Employee Stock Purchase Plan
• Potential eligibility for discretionary bonuses or commission payments
• Potential relocation assistance