Physical Design Engineer

Apple • Cupertino, CA

3d • $174,149 - $225,300

About The Position

Apple Inc. is hiring a Physical Design Engineer for work in Cupertino, California, and various unanticipated locations throughout the USA. The role works with logic design teams to understand partition architecture and drive physical design considerations early in the design cycle. The engineer completes netlist-to-GDS2 implementation for assigned partitions, meeting schedule and design goals, and owns timing, physical, and electrical verification through signoff closure.

The engineer resolves physical-design and flow issues, identifies solutions, and coordinates place-and-route work, goals, milestones, schedules, and dependencies across domains such as top-level design, STA, and block place and route. The role also develops and streamlines methodologies, best-known methods, guidelines, and checklists, and tracks execution and progress.

Responsibilities span frontend and backend implementation from RTL to GDS2, including synthesis, formal verification, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementation. The engineer performs hands-on physical implementation and timing closure for core platforms and SoCs, works with ASIC vendors, improves timing signoff criteria, analysis methodologies, and ECO-generation scripts, and drives physical design and timing convergence for high-frequency, low-power designs at block, cluster, or full-chip level. The work includes physical design closure of large, complex designs at 1GHz+ clock cycles. The position is 40 hours per week.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field.
• Experience and/or education using PNR tools such as ICC, ICC2, or Innovus for place and route, including floorplanning, placement, clock optimization, routing, and timing and power optimization for SoC partitions.
• End-to-end understanding of digital design implementation fundamentals, logic modeling, and hardware description languages used in digital IC design.
• Experience using TCL, Perl, Python, and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts to aid partition closure.
• Understanding of physical-design construction and analysis flows and methodologies sufficient to execute, close, and sign off SoC partitions.
• Understanding of transistors and digital circuits to make implementation, closure, and signoff trade-offs for SoC partitions.
• Understanding of digital logic and computer architecture fundamentals relevant to IC partitioning and resource planning.
• Understanding of results from physical-verification tools such as Calibre and generating fixes to address violations.
• Knowledge of signal behavior, interference effects, and noise-reduction principles relevant to high-speed digital circuits.

Responsibilities

• Work with logic design teams to understand partition architecture and drive physical design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Own timing, physical, and electrical verification and drive signoff closure for partitions.
• Resolve physical-design and flow issues, identify potential solutions, and drive their execution.
• Coordinate place-and-route work, including setting goals and milestones, planning short- and long-term work, and understanding dependencies across top-level design, STA, and block place-and-route domains.
• Develop and streamline physical-design methodologies and best-known methods, create guidelines and checklists, drive execution, and track progress.
• Drive timing closure through physical synthesis and place-and-route tools, working with ASIC vendors.
• Drive frontend and backend implementation from RTL to GDS2, including synthesis, FV, floorplanning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Improve timing signoff criteria and timing-analysis methodologies and flows, and develop or enhance ECO-generation scripts for timing closure.
• Drive floorplanning, physical synthesis, and physical-design closure for large, complex designs at 1GHz+ clock cycles.
• Drive physical-design and timing convergence for high-frequency, low-power designs at block, cluster, and/or full-chip level.

Benefits

• Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards.
• Ability to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain education expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.

What This Job Offers

• Job Type: Full-time