Physical Design Engineer

Apple • Cupertino, CA

1d • $216,200 - $324,800 • Onsite

About The Position

Apple Inc. is hiring a Physical Design Engineer to work with logic design teams on partition architecture and drive physical design decisions early in the design cycle. The role includes floor planning, pin assignments, macro placement and logic evaluation, and iterative placement optimization. The engineer conducts clock-tree synthesis, optimization, routing and post-route optimization, and completes netlist-to-GDS2 implementation for assigned partitions while meeting schedule and design goals.

The position is responsible for setup, hold, transition and static timing checks; Static Timing Analysis (STA); static IR and dynamic IVD analysis; power-related optimization and signoff; formal checking; full-chip timing closure; physical verification and closure; and signoff checklist closure. The engineer also partners with CAD teams to develop tools and methodologies that improve productivity and efficiency, and evaluates or develops physical-design-centric flows to improve leakage and dynamic power, area and performance.

Work includes top-level full-chip Place & Route implementation, complex IP-level partitions, block tiling, feed-through planning and pin assignment. The engineer collaborates with partition-level designers and cross-functional teams to determine design solutions. The position is based in Cupertino, California, and various unanticipated locations throughout the USA. It is 40 hours per week.

Requirements

• Bachelor's degree or foreign equivalent in Electronic Engineering, Electrical Engineering, Computer Engineering or a related field.
• Five years of progressive, post-baccalaureate experience in the job offered or a related occupation.
• Experience using Cadence Innovus and Synopsys ICC-2 for Place and Route of complex digital logic blocks.
• Experience using Primetime-SI to analyze timing results and generate necessary fixes.
• Ability to use Calibre to understand and debug physical verification results, including LVS, DRC and antenna checks.
• Understanding of UPF and knowledge of Conformal-LP to verify low-power intent.
• Experience using Voltus and Redhawk to generate and analyze EM and IR results for power-grid integrity, and generate fixes for reported violations.
• Knowledge of TCL, Python and TCSH for developing automation scripts that improve efficiency.
• Experience using Innovus CCOPT to analyze and optimize clock trees to minimize power and improve latency and skew.

Responsibilities

• Work with logic design teams to understand partition architecture and drive physical design aspects early in the design cycle.
• Conduct floor planning, pin assignments, macro placement and logic evaluation, and iterate on placement to optimize it.
• Conduct clock-tree synthesis, optimization, routing and post-route optimization.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Perform setup, hold, transition and static timing checks, and complete Static Timing Analysis (STA).
• Run static IR and dynamic IVD analysis, perform power-related optimization and signoff.
• Perform formal checking and signoff, full-chip timing closure, physical verification and closure, and signoff checklist closure.
• Partner with CAD teams to develop tools and methodologies that improve physical-design productivity and efficiency.
• Evaluate and/or develop physical-design-centric flows and methodologies to improve leakage and dynamic power, area and performance.
• Work on top-level full-chip Place & Route implementation, complex IP-level partitions, block tiling, feed-through planning and pin assignment.
• Collaborate with partition-level designers and cross-functional teams to determine the best design solution.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments and relocation.
• Opportunity to receive discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior