Physical Design Engineer

Broadcom • San Jose, CA

7d

About The Position

The Physical Design Engineer works on design implementation activities related to place and route and/or timing closure, including floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC). The role drives tools and methodologies to achieve desired PPA metrics, completes equivalence checks and power optimization, and implements timing and functional ECOs. The engineer applies Broadcom's design methodology and milestone flow to meet its criteria for achieving right-first-time silicon.

Requirements

• Primary expertise in place and route and/or timing, including constraints and STA.
• Proficiency in design implementation activities at both block and SoC level.
• Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
• Good problem-solving skills.
• Ability to work independently as a self-starter.
• Experience working in a global team and dynamic environment.
• Ability to learn and adapt to new tools and methodologies quickly.
• Excellent communication skills.
• A BS in Electrical Engineering, Computer Engineering, or a related field and 12 or more years of related experience; or an MS in Electrical Engineering, Computer Engineering, or a related field and 10 or more years of related experience.

Nice To Haves

• Extensive experience in floor-planning, partitioning, placement, clock tree synthesis, routing, and physical verification and/or constraints development, constraints validation, timing analysis, and closure.
• Experience with formal verification, timing analysis, and ECO implementation.
• Experience with tools such as PrimeTime, ICC2, Innovus, Caliber, and LEC.
• Full-chip tapeout experience with 7nm and lower technologies.

Responsibilities

• Perform design implementation activities related to place and route and/or timing closure.
• Carry out floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification (LVS/DRC).
• Drive tools and methodologies to achieve desired PPA metrics.
• Complete equivalence checks, static timing analysis (STA), timing closure, and power optimization.
• Implement timing and functional ECOs.
• Apply Broadcom's design methodology and milestone flow to meet criteria for achieving right-first-time silicon.

Benefits

• Discretionary annual bonus eligibility.
• Competitive new-hire equity grant and annual equity awards, subject to relevant plan documents and award agreements.
• Medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP).
• Employee Assistance Program (EAP).
• Company-paid holidays.
• Paid sick leave and vacation time.
• Paid Family Leave and other leaves of absence in accordance with applicable laws.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior