Design Verification Engineer

Apple • Austin, TX

12h

About The Position

Apple Inc. is hiring a Design Verification Engineer in Austin, Texas. The role focuses on understanding high-efficiency SoC architecture and a broad range of SoC components and subsystems, including standard peripherals, memory management, low-power specifications, multiprocessor systems, DDR, PCIe, memory controllers, USB, PLLs, power-up, and secure boot schemes.

The engineer will develop coverage-driven verification plans from specifications, review and refine plans to meet coverage targets, and create IP-level module and subsystem verification plans, testbenches, portable testbenches, sequences, and test infrastructure. The role also involves architecting reusable UVM-based testbenches, integrating multi-instance VIPs and subsystem testbenches into SoC-level test suites, and collaborating with design, architecture, software, firmware, external IP delivery teams, and DV methodology architects to integrate and verify SoC designs and improve verification flows. The stated schedule is 40 hours per week.

Requirements

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field.
• Experience and/or education using Verilog and VHDL to develop digital designs.
• Experience and/or education using SystemVerilog to develop digital-design testbenches, including reference models, stimulus generation, and debugging the design under test.
• Experience and/or education writing programs and designing system models using object-oriented programming in C/C++.
• Knowledge of combinational and sequential circuit designs and their usage patterns to understand, verify, and debug digital designs.
• Understanding of microprocessor architecture, processor organization, instruction set architecture, and assembly instructions for microprocessor design verification and integration.
• Understanding of CPU architecture related to multithreading, interrupt handling, semaphores, and use of these features in SoCs.
• Experience and/or education using Linux/Unix operating systems to manage files, run commands, and monitor jobs.
• Experience and/or education using Perl, Bash, and Python scripting to automate jobs and write programs supporting verification flows.
• Experience and/or education using industry-standard Cadence and Synopsys simulators to design digital blocks, simulate testbenches, and debug waveforms.

Responsibilities

• Understand high-efficiency SoC architecture and components including SPI, I2C, UART, timers, DMA, memory management, low-power specifications, multiprocessor systems, DDR, PCIe, memory controller subsystems, USB, PLLs, power-up, and secure boot schemes.
• Create coverage-driven verification plans from specifications, and review and refine them to achieve coverage targets.
• Create IP-level module and subsystem verification plans, testbenches, portable testbenches, sequences, and test infrastructure.
• Architect highly reusable UVM-based testbenches.
• Integrate complex multi-instance VIPs, subsystem testbenches, and test suites to the SoC level and achieve targeted coverage.
• Work with design, architecture, software, firmware, and external IP delivery teams to integrate and verify the overall SoC design efficiently.
• Collaborate with DV methodology architects to improve the verification flow.

What This Job Offers

• Job Type: Full-time