Design Verification Engineer

Apple•Cupertino, CA
•$174,149 - $225,300

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role works closely with architecture and RTL designers to verify design functionality and correctness. The engineer develops and leads test plans and test environments, creates complex tests in assembly, C, or vectors, and develops coverage monitors and analyzes coverage to confirm that test plans are fully exercised. The position also develops checkers or C-based transactors to verify designs. The position is 40 hours per week. The stated base pay range is $174,149–$225,300 per year; actual pay depends on skills, qualifications, experience, and location. Apple employees may participate in discretionary stock programs, including restricted stock unit awards and an Employee Stock Purchase Plan. Benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain education expenses related to career advancement. The role might also be eligible for discretionary bonuses or commission payments and relocation.

Requirements

  • Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or a related field.
  • Understand CPU architecture and system-level behavior to architect robust, high-quality verification strategies.
  • Apply root-cause failure analysis, waveform and log debugging, and drive targeted RTL or testbench fixes.
  • Develop testbenches, including transactors, bus functional models (BFMs), and protocol agents.
  • Design and deploy architectural and micro-architectural checkers to detect corner cases.
  • Own coverage-driven verification (CDV), including functional, assertion, and cross-coverage analysis, to sign off verification completeness.
  • Apply validation techniques such as formal property verification, hardware emulation, and FPGA/SoC bring-up flows.
  • Use verification languages and simulation or emulation tools such as C++, SystemVerilog, Python, or Verdi.
  • Know security vulnerabilities such as Spectre or Meltdown that impact modern processors.
  • Develop directed and constrained-random stimulus to stress pipelines, predictors, ALUs, register files, hazard units, crossbars, and performance scenarios.
  • Understand RTL for modern CPU predictors such as TAGE branch predictors, and develop golden models to verify the design.

Responsibilities

  • Work closely with architecture and RTL designers to verify design functionality and correctness.
  • Develop and lead test plans and test environments.
  • Develop complex tests in assembly, C, or vectors according to test plans.
  • Develop coverage monitors and analyze coverage to ensure test cases in plans are covered.
  • Develop checkers or C-based transactors to verify designs.

Benefits

  • Comprehensive medical and dental coverage
  • Retirement benefits
  • Discounted products and free services
  • Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple
  • Opportunity to participate in discretionary employee stock programs
  • Discretionary restricted stock unit awards
  • Ability to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan
  • Possible eligibility for discretionary bonuses or commission payments
  • Possible relocation
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