Design Verification Engineer

Apple • Cupertino, CA

13h • $187,408 - $225,300

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role ensures high-quality silicon for IC chips and IPs by reviewing specifications, creating verification plans, and executing verification activities to support tape-out.

The engineer verifies power-management IP, including mixed-signal circuits, LDOs, data converters, references, input-output circuits, and clock circuits. The work includes verifying mixed-signal IC designs through simulations that combine analog circuits, Verilog-AMS modules, and Verilog RTL. The engineer carries verification plans from beginning to end, including testbench and environment bring-up, regressions, and failure debugging, and develops scalable and portable verification methodologies and environments.

The verification environment may include stimuli, checkers, assertions, trackers, and coverage. The position is 40 hours per week. The base pay range is $187,408–$225,300 per year, depending on skills, qualifications, experience, and location. Apple also describes employee stock programs, medical and dental coverage, retirement benefits, discounted products and services, education-expense reimbursement for qualifying career-related formal education, and possible discretionary bonuses or commission payments and relocation.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electronics and Communication Engineering, Computer Engineering, or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• Experience using hardware description languages, including Verilog, SystemVerilog, or Verilog-AMS, to understand issues in digital designs and models.
• Experience designing and developing verification plans using analog design, verification, and debugging to identify design issues and verify analog IP before production.
• Understanding of mixed-signal design and experience developing and executing verification plans and debugging complex mixed-signal IP before production.
• Experience writing test patterns and plans using EDA tools such as Cadence and Synopsys.
• Experience running mixed-signal simulations and debugging issues with Cadence or Synopsys AMS simulation tools to identify functional issues in IP defined by specification documents.
• Experience with verification methodologies and tools, including simulators, waveform viewers, or execution automation, to ensure complete verification coverage.
• Experience running simulations and using Cadence or Synopsys viewers to observe outputs.
• Experience evaluating and benchmarking Cadence analog and mixed-signal simulators and analyzing simulator accuracy, strengths, and limitations.
• Experience debugging and resolving issues in Cadence analog and mixed-signal simulation environments.
• Experience reproducing and triaging tool-user issues by recreating simulation scenarios and design configurations, performing root-cause analysis, and driving resolution with R&D teams.

Responsibilities

• Ensure high-quality silicon for IC chips and IPs.
• Review specifications and create verification plans.
• Execute verification according to plan to support tape-out.
• Verify power-management IP, including mixed-signal circuits, LDOs, data converters, references, input-output circuits, and clock circuits.
• Verify mixed-signal IC designs through simulations using analog circuits, Verilog-AMS modules, and Verilog RTL.
• Execute verification plans end to end, including testbench and environment bring-up, regressions, and failure debugging.
• Develop verification methodologies suited to the IP and designed for scalability and portability.
• Develop verification environments, including stimuli, checkers, assertions, trackers, and coverage.
• Evaluate and benchmark Cadence analog and mixed-signal simulators and analyze their accuracy, strengths, and limitations.
• Debug simulator issues and distinguish tool-level defects from design-level issues to support root-cause analysis and simulation integrity.
• Reproduce and triage issues reported by tool users, conduct root-cause analysis, and drive resolution with R&D teams.

Benefits

• Opportunity to participate in discretionary Apple employee stock programs.
• Eligibility for discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through voluntary participation in the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Possible discretionary bonuses or commission payments.
• Possible relocation.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level