Design Verification Engineer

Apple • Beaverton, OR

5d

About The Position

Apple is seeking a hardworking Design Verification Engineer to help deliver fully functional first silicon for IP designs and craft future products. The role covers all phases of pre-silicon verification for part of an SoC or IP, from establishing verification methodology and developing test plans to building verification environments, writing tests, debugging, measuring coverage, and supporting sign-off for RTL freeze and tape-out.

The engineer will develop detailed test and coverage plans based on microarchitecture and create scalable, portable verification methodologies and environments. Environment components include stimulus, checkers, assertions, trackers, and coverage. Responsibilities also include bringing up the design and verification environment, enabling regressions, executing verification plans, debugging test failures, developing block-, IP-, and SoC-level testbenches, and tracking and reporting verification progress using metrics such as bugs and coverage. The role also calls for using LLMs and related technologies to improve execution efficiency and quality.

Requirements

• Bachelor’s degree in a technical subject area.
• At least 3 years of relevant industry experience.

Nice To Haves

• Master’s degree in a technical subject area and relevant industry experience.
• Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
• Strong knowledge of developing scalable and portable testbenches.
• Proven experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Experience with power-aware (UPF) or similar verification methodology.
• Knowledge of a scripting language such as Python, Perl, or TCL.
• Some experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR; this is a plus but not required.
• Knowledge of formal verification methodology; this is a plus but not required.

Responsibilities

• Ensure bug-free first silicon for a portion of an SoC or IP.
• Establish verification methodology and develop detailed test and coverage plans based on microarchitecture.
• Develop scalable and portable verification environments, including stimulus, checkers, assertions, trackers, and coverage.
• Write tests and execute verification plans.
• Perform design bring-up and verification-environment bring-up, enable regressions, and debug test failures.
• Develop block-, IP-, and SoC-level testbenches.
• Track and report verification progress using metrics including bugs and coverage.
• Use LLMs and related technologies to improve execution efficiency and quality.
• Support sign-off for RTL freeze and tape-out.

What This Job Offers

• Job Type: Full-time