Design Verification Engineer

Apple • Beaverton, OR

8d

About The Position

Apple is seeking a hardworking Design Verification Engineer to help deliver fully functional first silicon for IP designs and contribute to upcoming products. The role covers pre-silicon verification from methodology and test-plan development through verification-environment development, test writing, debugging, coverage, and sign-off for RTL freeze and tape-out. The engineer will be responsible for verifying part of an SoC or IP and developing detailed test and coverage plans based on its microarchitecture. They will create scalable, portable verification environments and components such as stimulus, checkers, assertions, trackers, and coverage. The role also involves bringing up designs and DV environments, enabling regressions, investigating failures, closing bugs, developing block-, IP-, and SoC-level testbenches, and tracking and reporting progress through metrics such as bugs and coverage. The engineer is expected to use LLMs and related technologies to improve verification efficiency and quality.

Requirements

• Bachelor's degree in a technical subject area.
• A minimum of 10 years of relevant industry experience.
• Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
• Deep knowledge of developing scalable and portable testbenches.
• Strong experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Experience with power-aware (UPF) or similar verification methodology.
• Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

• Experience with serial protocols such as PCIe or USB, or a parallel protocol such as DDR.
• Knowledge of formal verification methodology.
• Knowledge of emulation for verification technologies.

Responsibilities

• Study design specifications and create test plans.
• Establish verification methodology suitable for the IP, with a scalable and portable environment.
• Develop verification plans for features under their responsibility and execute those plans.
• Develop SystemVerilog/UVM infrastructure and testbenches to stress the design.
• Build verification-environment components, including stimulus, checkers, assertions, trackers, and coverage.
• Perform design and DV-environment bring-up and enable regressions.
• Develop tests and debug regression failures; fix failures and close bugs.
• Carry out coverage activities and sign-off for RTL freeze and tape-out.
• Develop block-, IP-, and SoC-level testbenches.
• Track and report DV progress using metrics including bugs and coverage.
• Use LLMs and related technologies to improve execution efficiency and verification quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior