Design Verification Engineer

Apple

23h

About The Position

As a member of Apple’s design verification group, the Design Verification Engineer helps produce fully functional first silicon for IP designs. The role covers all phases of pre-silicon verification, from establishing methodology and developing test plans to building verification environments, writing tests, debugging, tracking coverage, and signing off for RTL freeze and tape-out.

The engineer is responsible for ensuring bug-free first silicon for part of an SoC or IP. They develop detailed test and coverage plans based on microarchitecture and create scalable, portable verification methodologies and environments. Environment components include stimulus, checkers, assertions, trackers, and coverage. The role also involves executing plans, bringing up designs and DV environments, enabling regressions, debugging failures, developing block-, IP-, and SoC-level testbenches, and reporting progress through metrics such as bugs and coverage. Use of LLMs and related technologies is expected to improve execution efficiency and quality.

Requirements

• BS degree in a technical subject area and at least 3 years of relevant industry experience, or equivalent.
• Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
• Strong knowledge of developing scalable and portable testbenches.
• Proven experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Knowledge of a scripting language such as Python, Perl, or TCL.

Nice To Haves

• MS degree in a technical subject area and relevant industry experience is strongly preferred.
• Experience with power-aware (UPF) or similar verification methodology.
• Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
• Knowledge of formal verification methodology.

Responsibilities

• Establish design verification methodology suitable for the IP, with a scalable and portable environment.
• Develop detailed verification test and coverage plans based on the microarchitecture.
• Develop verification environments and components, including stimulus, checkers, assertions, trackers, and coverage.
• Execute verification plans, including design bring-up and DV environment bring-up.
• Enable regression features and debug test failures.
• Develop block-, IP-, and SoC-level testbenches.
• Track and report DV progress using metrics including bugs and coverage.
• Complete pre-silicon verification activities and sign off for RTL freeze and tape-out.
• Use LLMs and related technologies to improve execution efficiency and quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level