Design Verification Engineer

Microsoft • Raleigh, NC

1d • $102,100 - $202,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies for Microsoft’s online businesses and Azure platform. The Compute Silicon & Manufacturing Engineering team helps define and deliver operational measures of success for hardware manufacturing, including quality, delivery, scale, planning, and sustainability. The team seeks engineers to develop customer-focused technical solutions that manage and optimize cloud infrastructure.

The Design Verification Engineer will be part of a pre-silicon verification and post-silicon validation team developing custom silicon components. The role involves creating verification environments and infrastructure, driving functional coverage to closure, and collaborating across engineering and vendor teams to ensure comprehensive pre- and post-silicon testing.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Must provide citizenship, U.S. residency, or other protected-status documentation to assess eligibility for access to export-controlled information; citizenship is verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or master's degree in one of these fields and at least 3 years of technical engineering experience; or bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• At least 3 years of pre-silicon SoC, chip-level, subsystem, or IP verification experience.
• At least 3 years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/OVM, and coverage-based verification.
• At least 3 years of experience with SystemVerilog, C/C++, and scripting languages such as Python, Ruby, or Perl.
• Experience with one or more of coherency, caches, fabrics, DDR controllers, PCIe, CXL, AXI/CHI protocol bridges, or other complex IP, blocks, or subsystems.
• Experience across a full product cycle from definition to silicon, including writing IP/block or subsystem-level test plans, developing tests, debugging failures, and coverage signoff.
• Experience creating, maintaining, or integrating test benches, checkers, and stimulus using SVTB, UVM, Formal Verification, and/or C/C++.
• Experience automating verification processes using Python or another scripting language.

Responsibilities

• Contribute to pre-silicon verification and post-silicon validation for custom silicon components.
• Write constrained-random stimulus, scoreboards, checkers, and assertions to verify design correctness.
• Develop Verification IP (VIP) components for internally developed designs.
• Develop Universal Verification Methodology (UVM) components that interface test code with verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management, and third-party vendor teams to ensure comprehensive pre- and post-silicon testing.
• Develop scripts for verification and validation infrastructure.

Benefits

• Certain roles may be eligible for benefits and other compensation; additional benefits and pay information is provided via the linked Microsoft careers page.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level