Design Verification Engineer

Microsoft • Raleigh, NC

1d • $102,100 - $219,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) builds and operates the infrastructure and foundational technologies behind Microsoft’s online services and Azure platform. The Compute Silicon & Manufacturing Engineering team helps deliver high-quality, timely, cost-effective cloud hardware while improving manufacturing planning, quality, delivery, scale, and sustainability. The Design Verification Engineer joins a team developing custom silicon components and contributes to pre-silicon verification and post-silicon validation, verification infrastructure, and collaboration across hardware and software teams.

Requirements

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or a bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Provide proof of citizenship, U.S. residency, or other protected status as required to assess eligibility for access to export-controlled information; citizenship must be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or a master's degree in one of these fields and at least 3 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
• At least 3 years of pre-silicon System on Chip (SoC), chip-level, subsystem, or IP verification experience.
• At least 3 years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/OVM, and coverage-based verification.
• At least 3 years of experience with SystemVerilog, C/C++, and scripting languages such as Python, Ruby, or Perl.
• Demonstrated experience in one or more of the following: coherency, caches, fabrics, DDR controllers, PCIe, CXL, AXI/CHI protocol bridges, or other complex IP, blocks, or subsystems.
• Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem-level test plans, developing tests, debugging failures, and coverage signoff.
• Experience creating, maintaining, or integrating testbenches, checkers, and stimulus using SVTB, UVM, formal verification, and/or C/C++.
• Experience automating verification processes using Python or another scripting language.

Responsibilities

• Establish a role on a pre-silicon verification and post-silicon validation team developing custom silicon components.
• Write constrained-random stimulus, scoreboards, checkers, and assertions to verify design correctness.
• Develop Verification IP (VIP) components for custom designs.
• Develop Universal Verification Methodology (UVM) components that interface between test code and verification simulation environments.
• Define and implement functional coverage and drive coverage closure.
• Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management, and third-party vendor teams to ensure comprehensive pre- and post-silicon testing.
• Develop scripts for verification and validation infrastructure.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level