Design Verification Engineer

Microsoft•Raleigh, NC

3d•$102,100 - $219,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for powering Microsoft’s “Intelligent Cloud” mission by delivering the core infrastructure and foundational technologies for Microsoft's online businesses. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE focuses on the design, development, manufacturing, and packaging of Microsoft's computer chips, such as Azure Cobalt. The Shared and Custom IP & Silicon (SCIPS) team is crucial in defining and delivering operational measures of success for hardware manufacturing, aiming to improve planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware. This role is within the SCIPS team, seeking engineers passionate about customer-focused solutions and future technical implementations for cloud infrastructure management and optimization.

Requirements

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Must pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Must provide proof of country of citizenship or US residency or other protected status for assessment of eligibility to access export-controlled information.
Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Nice To Haves

3+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience in executing pre-silicon verification of IPs/Sub Systems/SoCs through full cycle.
Background in creating and debugging IP/SoC Level tests in SV-UVM/C.
In depth knowledge of verification principles, testbenches and stimulus generation.
Solid understanding of silicon chip and/or computer architecture
Scripting language such as Python, Ruby or Perl.
Experience with the use of formal verification methods
Experience in Assembly, start up code and linker scripts
Experience in developing Makefiles for software development.

Responsibilities

Plan the verification of complex design IP interacting with the architecture and design engineers to identify verification test scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
Develop tests using UVM or C/C++
Analyze and debug test failures with designers to deliver functionally correct design.
Identify and write functional coverage for stimulus and corner cases.
Close coverage to plug verification holes and meet tape-out requirements.
Collaborate with cross-functional teams, including Architecture, Design, Verification and FW to deliver products with key differentiators.
Engage in chip bring-up activities and write test firmware to assist other teams.
Drive innovation by enhancing validation efficiency through new methodologies and tools.
Embody Microsoft’s core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive Results, Influence for Impact, Judgement, and Diversity & Inclusion.