Design Verification Engineer

Texas Instruments•Dallas, TX

About The Position

This Design Verification Engineer role offers the opportunity to drive, define, and utilize industry leading design verification methodologies, tools, and flows to ensure that differentiated SoCs and IP meet all functional and quality specifications. You will be expected to learn the SoC/IP functionality and the system context to build comprehensive verification test plans and milestone-based schedules. This role offers the opportunity to learn the complex SoC development process and interact with various functional teams spanning systems, design, software, and applications. The set of IPs covers Multimedia IPs, Vision IPs, Data movement IPs, interconnect, safety, security, Realtime functionality and broader infrastructure IPs to help develop Embedded Processors. You will work with an IP DV team driving verification while helping to find innovative solutions to customers’ problems through “out of the box thinking” to deliver highly differentiated products. Candidates must have both good communication skills and solid digital design verification experience. IP design verification team will have a charter to verify infrastructure IP’s enabling automotive and industrial processors. You will interface with various engineering teams within Processor including SoC design, verification, validation, test, systems, SW, applications and marketing to successfully help verify new IPs from concept to design. Expertise in Data movement and bus protocols (AMBA, OCP etc) is must and knowledge of interrupt, security, safety, coherence is desirable. You will be a core member in the IP design team driving flawless execution.

Requirements

Bachelor’s degree in Electrical/Computer Engineering, Computer Science, or a related field.
10+ years of experience in Design Verification (DV) or Design development.
Expertise in data movement, SoC integration concepts, and bus protocols (e.g., AMBA: AXI, CHI, AHB, APB, etc.), with exposure to DMA, Cache, ARM CPU cores, and DDR as well as proficiency in Verilog.
Experience with simulation tools (e.g., NCsim), code coverage, and debug tools

Nice To Haves

A strong understanding of digital functionality and exposure to digital design methodologies.
The ability to derive a DV plan and support existing designs, even when working with sparse legacy documentation.
Familiarity with verification environments to actively participate in functional debugging.
Ability to take initiative and drive results while working with team members across various time zones.
Proven ability to own design deliverables and manage schedules.
Strong problem-solving skills using a systematic approach.
Experience with SystemVerilog and VHDL.
In-depth knowledge of bus protocols, including AXI, CHI, AHB, APB, and OCP.
Proficiency in scripting languages such as Tcl, Perl, and Python.
Experience with silicon debug using Automated Test Equipment (ATE) and bench characterization environments.
Strong analytical and systematic problem-solving skills.
Excellent verbal and written communication skills.
Ability to work collaboratively within cross-functional teams.
Strong time management skills with a proven track record of on-time project delivery.
Ability to thrive in a fast-paced and rapidly changing environment.
Proven ability to take initiative and drive results.

Responsibilities

Architecting, developing, and driving module and system-level test strategies, performance validation, verification plans, testbenches, functional models, and test cases.
Promoting and advancing verification methodologies for complex digital logic using C/UVM testbenches, ranging from block-level to full system/SoC.
Creating, executing, enhancing, and debugging simulation test cases using coverage-driven, constrained-random stimulus.
Defining and implementing functional coverage and driving coverage closure.
Debugging complex designs to identify the root cause of problems.
Collaborating across verification teams to promote the reuse of components.
Verifying SoCs in emulation environments and performing post-silicon verification, characterization, and debug.
Interfacing with third-party vendors to help drive delivery milestones and quality.
Working closely with IP verification teams to help build IP verification plans and tests, and to support functional debugging.
Supporting IP during silicon bring-up activities, test program development, customer engagement, and silicon/application debug.