Design Verification Engineer

Apple•San Diego, CA

11h

About The Position

At Apple, the Design Verification Engineer helps verify IP designs to enable fully functional first silicon. The role covers pre-silicon verification, including establishing verification methodology, developing test plans and verification environments, writing tests, debugging, collecting coverage, and signing off for RTL freeze and tape-out. The engineer is responsible for verifying part of the SoC or IP and developing detailed test and coverage plans from its microarchitecture. They create scalable, portable verification methodologies and environments with components such as stimulus, checkers, assertions, trackers, and coverage. The role also involves bringing up designs and DV environments, enabling regressions, debugging failures, developing block-, IP-, and SoC-level testbenches, and tracking and reporting progress using metrics such as bugs and coverage. The engineer is expected to use LLMs and related technologies to improve efficiency and quality.

Requirements

Bachelor's degree in a technical subject area with at least 10 years of proven experience, or equivalent.
Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
Deep knowledge of developing scalable and portable testbenches.
Strong experience with verification methodologies and tools, including simulators, waveform viewers, build-and-run automation, coverage collection, and gate-level simulations.
Working experience using LLMs for efficiency and quality.
Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

Experience with power-aware (UPF) or similar verification methodology.
Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
Knowledge of formal verification methodology.
Knowledge of emulation technologies for verification.

Responsibilities

Ensure bug-free first silicon for part of the SoC or IP.
Develop detailed test and coverage plans based on the microarchitecture.
Establish verification methodology appropriate to the IP and ensure the environment is scalable and portable.
Develop verification environments, including stimulus, checkers, assertions, trackers, and coverage.
Develop and execute verification plans for assigned features.
Perform design bring-up and DV environment bring-up, enable regressions, and debug test failures.
Develop block-, IP-, and SoC-level testbenches.
Track and report DV progress using metrics including bugs and coverage.
Use LLMs and related technologies to improve execution efficiency and quality.
Complete verification sign-off for RTL freeze and tape-out.