Design Verification Engineer

Apple

11h

About The Position

The Design Verification Engineer will participate in the verification process for a large-scale SoC. The role involves developing verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors. The engineer will apply advanced techniques to achieve high-quality, productive verification and meet time-to-market goals, while working closely with the design team to support timely delivery of quality designs. The position is relevant to Apple’s Herzliya, Haifa, and Jerusalem sites.

Requirements

• At least 5 years of experience in SoC or IP verification.
• Advanced knowledge of SoC architecture and design, in-depth knowledge of verification flows, and a broad system view.
• Deep understanding of and demonstrated experience with advanced verification processes, including coverage-driven and formal methods.
• Extensive experience with SystemVerilog and UVM.
• Experience developing verification infrastructure.
• Scripting and programming experience using several of Perl, Python, Verilog, SystemVerilog, C, C++, and TCL.
• B.Sc. or M.Sc. in Electrical or Computer Engineering.

Nice To Haves

• Knowledge of storage IPs and control-oriented design.
• Knowledge of formal methods and hardware acceleration.

Responsibilities

• Participate in verification of a large-scale SoC.
• Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors.
• Apply advanced techniques to improve verification quality, productivity, and time-to-market.
• Work with the design team to support timely delivery of quality designs.
• Work with methods to accelerate verification time.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level