Design Verification Engineer

Intel•Austin, CA

12d•Hybrid

About The Position

Intel is seeking a Design Verification Engineer for its Silicon Chassis team. The role contributes to verification of next-generation interconnect and chassis IPs that scale across multiple product families. Working closely with senior engineers, the engineer will help develop and execute robust verification plans, create reusable verification environments, and support first-pass silicon success through strong design verification practices. The position calls for programming and algorithmic problem-solving skills, hands-on verification development, and flexibility to work across traditional discipline boundaries. AI-assisted workflows are part of everyday development. The engineer will work with architecture, design, and software teams on specification reviews, feature clarification, bug triage, and closure. The role contributes to simulation and formal verification, functional coverage planning and closure, quality signoff under technical-lead guidance, and ongoing improvements to verification automation, regression quality, and development efficiency.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 5+ years of industry experience, or a Master's degree with 4+ years of relevant experience.
Programming fundamentals and algorithmic problem-solving skills, with demonstrated hands-on coding experience in SystemVerilog, C/C++, and Python.
Foundation in simulation-based verification methodologies (UVM/ABV), with exposure to formal verification concepts; testbench development, debugging, and coverage-driven verification.
Hands-on experience using AI-assisted development tools as part of daily workflows for coding, debugging, and test development.
Exposure to interconnects and bus protocols, for example AMBA AXI/ACE/CHI, PCIe, CXL, or UCIe.
Ability to write clean, reusable, and maintainable verification code and automation scripts, and collaborate effectively across architecture, design, and software teams.

Nice To Haves

Understanding of cache coherency and memory consistency models.
Experience with external interfaces and system integration debug.
Experience with formal verification tools such as JasperGold, VC Formal, or similar, and emulation or FPGA-based verification.
Exposure to RTL concepts, physical design, or CAD tool flows.
Prior work with system IPs such as MMUs, SMMU or IOMMU, and interrupt controllers.

Responsibilities

Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level.
Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity.
Work with architecture, design, and software teams on specification reviews, feature clarification, bug triage, and closure; contribute outside strict design verification boundaries when needed.
Analyze simulation failures, quickly root-cause issues, and drive fixes to closure with clear technical communication.
Contribute to functional coverage planning, coverage closure, and quality signoff under guidance of technical leads.
Contribute to simulation and formal verification efforts.
Continuously improve verification automation, regression quality, and development efficiency.
Write clean, reusable, and maintainable verification code and automation scripts, and collaborate effectively across architecture, design, and software teams.