Design Verification Engineer

Apple

About The Position

Apple is seeking a Design Verification Engineer to help deliver fully functional first silicon for IP designs and parts of the SoC/IP. The role covers all phases of pre-silicon verification, from defining verification methodology and developing test plans to building verification environments, writing tests, debugging, tracking coverage, and supporting RTL freeze and tape-out sign-off. The engineer will develop scalable, portable verification methodologies and environments suited to the IP, including stimulus, checkers, assertions, trackers, and coverage. The role includes creating and executing verification plans based on microarchitecture, bringing up designs and DV environments, enabling regressions, debugging failures, and tracking and reporting progress using metrics such as bugs and coverage. The engineer will also use LLMs and related technologies to improve execution efficiency and quality, and will learn to develop block-, IP-, and SoC-level testbenches.

Requirements

Bachelor’s degree in a technical subject area and at least 3 years of relevant industry experience, or equivalent.
Strong knowledge of object-oriented programming, SystemVerilog, and UVM.
Strong knowledge of developing scalable and portable testbenches.
Proven experience with verification methodologies and tools, such as simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulations.
Working experience using LLMs for efficiency and quality.
Knowledge of a scripting language such as Python, Perl, or Tcl.

Nice To Haves

Master’s degree in a technical subject area and relevant industry experience are strongly preferred.
Experience with power-aware (UPF) or similar verification methodology.
Some experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
Knowledge of formal verification methodology.

Responsibilities

Ensure bug-free first silicon for a part of the SoC/IP.
Develop detailed test and coverage plans based on the microarchitecture.
Establish scalable and portable verification methodologies suitable for the IP.
Develop verification environments and components, including stimulus, checkers, assertions, trackers, and coverage.
Develop and execute verification plans for assigned features.
Perform design bring-up and DV environment bring-up.
Enable regression features and debug test failures.
Develop block-, IP-, and SoC-level testbenches.
Track and report DV progress using metrics including bugs and coverage.
Use LLMs and related technologies to improve execution efficiency and quality.
Support sign-off for RTL freeze and tape-out.