Design Verification Engineer

Broadcom•San Jose, CA

About The Position

The ASIC Product Division at Broadcom is seeking a qualified Design Verification Engineer to support SoC and IP development programs. The engineer will join a high-performance design team developing state-of-the-art subsystems to meet customer requirements. The position focuses on developing verification environments and components, creating tests and coverage, and debugging simulation results at system and block levels.

Requirements

  • Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
  • 12+ years of relevant industry work experience.
  • Experience verifying designs at system and block levels.
  • Fluent knowledge of RTL verification methodologies, including SystemVerilog.
  • Strong experience with ASIC design verification flows and DV methodologies.
  • Strong working knowledge of object-oriented verification languages such as OVM and UVM, C/C++, Perl, and scripting.
  • Strong independent design-debugging capability.
  • Strong verbal and written communication skills.
  • Ability to work comfortably in a team environment with verification and design team members.
  • Demonstrated ability to analyze and resolve complex verification trade-off scenarios.
  • Highly productive individual contributor with demonstrated technical capability in system and sub-block-level verification.
  • Must have legal authorization to work in the United States.

Nice To Haves

  • Experience with hardware design and debug, C++/SystemC, and other programming languages.
  • Experience working with emulators and FPGA-based prototyping.
  • Familiarity with overall chip design methodologies and tools.
  • Knowledge of CPU, DDR, bus protocol, network protocol, or DSP design.

Responsibilities

  • Develop verification environments using modern verification techniques, including SystemVerilog and UVM.
  • Design verification components such as UVM agents and behavioral models.
  • Implement coverage and assertions using SystemVerilog.
  • Develop random and directed test cases based on specifications.
  • Analyze and debug simulation failures and analyze coverage results.

Benefits

  • Discretionary annual bonus eligibility.
  • Opportunity to receive a competitive new-hire equity grant and annual equity awards.
  • Medical, dental, and vision plans.
  • 401(k) participation with company matching.
  • Employee Stock Purchase Program (ESPP).
  • Employee Assistance Program (EAP).
  • Company-paid holidays.
  • Paid sick leave and vacation time.
  • Paid Family Leave and other leaves of absence in accordance with applicable laws.
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service