Design Verification Engineer

Apple • Cupertino, CA

9h • $174,149 - $225,300

About The Position

Apple Inc. is hiring a Design Verification Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role is responsible for verifying complex digital IPs and collaborating with system architects and digital designers to make block-level specifications clear and precise. The engineer uses specifications to develop verification plans that exercise functional, performance, stress, and error-condition cases.

The role owns creation of verification test benches using formal verification and UVM-based simulation. It involves building SystemVerilog Assertions and constrained-random UVM test cases to achieve complete functional and code coverage. The engineer also participates in code reviews, helps develop precise design specifications for digital control blocks, creates block- and chip-level verification plans, and architects block-level verification elements. The position assists with chip- and system-level verification environments, develops drivers, tests, reference models, and checkers using SystemVerilog and UVM, debugs test failures with designers, and uses coverage to track progress and assess tape-out readiness.

The position is 40 hours per week. The listed base pay range is $174,149–$225,300 per year, depending on skills, qualifications, experience, and location. Apple describes benefits that include medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain career-related education expenses, including tuition. Employees may also be eligible to participate in discretionary stock programs, purchase Apple stock at a discount through the Employee Stock Purchase Plan, and receive discretionary bonuses or commission payments and relocation assistance, subject to eligibility and applicable plan terms.

Requirements

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field.
• Experience and/or education utilizing SystemVerilog to create block-level verification elements.
• Experience and/or education utilizing Verilog and VHDL to debug design issues and identify root causes of bugs.
• Experience and/or education utilizing digital hardware simulation to develop checkers and tests.
• Experience and/or education utilizing object-oriented programming and C to understand and debug firmware executions on chips.
• Experience and/or education utilizing Python, Perl, or algorithms to develop design verification automation flows.
• Experience and/or education utilizing chip simulations on CAD software, including debugging simulation failures for bug hunting.
• Finite State Machine design and verification experience to fully verify FSM designs.

Responsibilities

• Verify complex digital IPs.
• Work with system architects and digital designers to clarify and refine block-level specifications.
• Develop verification plans covering functional, performance, stress, and error-condition cases.
• Create verification test benches using formal verification and UVM-based simulation.
• Build SystemVerilog Assertions and constrained-random UVM test cases to achieve functional and code coverage.
• Participate in code reviews of other chip blocks and propose ways to improve the likelihood of bug-free designs at first tape-out.
• Collaborate on precise design specifications for digital control blocks.
• Create block- and chip-level verification plans from design specifications.
• Architect and create block-level verification elements.
• Assist in architecting chip- and system-level verification environments.
• Use SystemVerilog and UVM to develop drivers, tests, reference models, and checkers.
• Debug test failures and work with designers to develop fixes.
• Use functional and code coverage to track progress and assess tape-out readiness.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple
• Opportunity to participate in discretionary restricted stock unit awards
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan
• Possible discretionary bonuses or commission payments
• Possible relocation assistance

What This Job Offers

• Job Type: Full-time