Design Verification Engineer

Apple • San Diego, CA

2d

About The Position

As a Design Verification Engineer, you'll be at the center of our silicon design
group's verification efforts, ensuring the quality and reliability of
next-generation cellular systems. Working on innovative baseband modems and RF
link controllers for Apple's SOCs, you'll craft highly reusable UVM verification
environments that set the standard for quality and efficiency. You'll develop
comprehensive coverage-driven and directed test cases that thoroughly validate
complex IP and subsystem designs, working closely with multi-functional teams
throughout the process. In this role, you'll drive methodology innovation by
deploying sophisticated tools and techniques that elevate verification practices
and ensure tape-out readiness. Collaborating with product development teams
across Apple, you'll help deliver cellular systems that redefine industry
capabilities and enhance customer experiences globally. This position offers
exceptional opportunities to deepen your expertise across cellular protocols,
complex IP and subsystem architectures, advanced fabric protocols, and
sophisticated debug methodologies. You'll gain experience with best-in-class
design verification practices, co-verification techniques with models and
firmware, and industry-standard low-power architectures. We're looking for
engineers with hands-on ASIC design verification experience using reusable
verification methodologies such as UVM. The ideal candidate excels at detailed
test planning, adapts optimally to evolving requirements, knowledge of the
latest ML based tools to improve productivity and is driven to achieve the
highest quality standards. You thrive in collaborative environments and are
eager to address the verification challenges inherent in complex,
high-performance cellular systems. If you want to contribute to products that
impact customers worldwide while advancing your technical expertise, we'd love
to hear from you.

Requirements

• BS and a minimum of 10 years relevant industry experience
• Strong knowledge of System Verilog and UVM
• Skilled in System C, C/C++, Python/perl
• Highly proficient in developing and establishing DV Methodologies
• Experience in using LLMs and MCPs
• Experience with developing Python-based automation solutions
• Experience with constraint random testing, SVA, Coverage driven verification
• Strong test planning and problem-solving skills

Nice To Haves

• Master of Science degree in Electrical Engineering/Computer Science
• Experience in C/C++ modeling for design verification
• Knowledge of 4G/5G cellular physical layer operation (3GPP)
• Experience with verification of embedded processor cores
• Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment
• Experience using LLMs to improve efficiency and quality of verification
• Understanding of prompt engineering and LLM workflow optimization

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees