Design Verification Engineer

Apple • San Diego, CA

3h

About The Position

As a Design Verification Engineer, you will contribute to verification efforts for next-generation cellular systems, including baseband modems and RF link controllers for Apple SoCs. You will create reusable UVM verification environments and develop coverage-driven and directed test cases to validate complex IP and subsystem designs. You will work with cross-functional teams, introduce tools and techniques to improve verification methodology, and help ensure designs are ready for tape-out. The role involves collaboration with product development teams across Apple and provides opportunities to build expertise in cellular protocols, IP and subsystem architectures, fabric protocols, debug methodologies, co-verification with models and firmware, and low-power architectures. The role seeks engineers with hands-on ASIC design verification experience using reusable methodologies such as UVM, strong test-planning skills, adaptability to evolving requirements, familiarity with ML-based productivity tools, and a commitment to quality.

Requirements

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Strong knowledge of SystemVerilog and UVM.
• Skills in System C, C/C++, Python, and Perl.
• High proficiency in developing and establishing design verification methodologies.
• Experience using LLMs and MCPs.
• Experience developing Python-based automation solutions.
• Experience with constrained-random testing, SVA, and coverage-driven verification.
• Strong test-planning and problem-solving skills.

Nice To Haves

• Master of Science degree in Electrical Engineering or Computer Science.
• Experience in C/C++ modeling for design verification.
• Knowledge of 4G/5G cellular physical-layer operation (3GPP).
• Experience verifying embedded processor cores.
• Hands-on UVM verification experience with bus fabrics, NoCs, and AHB- or AXI-based bus architectures.
• Experience using LLMs to improve verification efficiency and quality.
• Understanding of prompt engineering and LLM workflow optimization.

Responsibilities

• Create reusable UVM verification environments for cellular baseband modems and RF link controllers.
• Develop coverage-driven and directed test cases to validate complex IP and subsystem designs.
• Collaborate with multifunctional and product development teams across Apple.
• Deploy tools and techniques to improve verification methodology and practices.
• Help ensure designs are ready for tape-out.
• Apply detailed test planning and verification practices to achieve high-quality results.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior