Design Verification Engineer

Microsoft•Raleigh, NC
•$102,100 - $219,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) powers Microsoft's expanding cloud infrastructure and supports its online businesses and Azure platform through server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE develops, manufactures, and packages Microsoft's computer chips, including Azure Cobalt. It supports the delivery of high-volume, high-quality, cost-effective cloud hardware while advancing planning, quality, delivery, scale, and sustainability. Microsoft is seeking a Design Verification Engineer to join a pre-silicon verification and post-silicon validation team working on custom silicon components. The role involves developing verification environments, stimulus, checkers, assertions, coverage, and infrastructure, and collaborating across engineering and vendor teams to ensure comprehensive testing.

Requirements

  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 1 year of technical engineering experience; or bachelor's degree in one of these fields and at least 2 years of technical engineering experience; or equivalent experience.
  • Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
  • Provide proof of citizenship, U.S. residency, or other protected status as required to assess eligibility for access to export-controlled information; citizenship will be verified with a valid passport, with other applicable documents accepted for lawful permanent residents, refugees, and asylees.

Nice To Haves

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field; or a master's degree in one of these fields and at least 3 years of technical engineering experience; or a bachelor's degree in one of these fields and at least 5 years of technical engineering experience; or equivalent experience.
  • At least 3 years of pre-silicon System on Chip (SoC), chip-level, subsystem, or IP verification experience.
  • At least 3 years of experience with verification principles, object-oriented programming, test plan development, testbench creation, stimulus generation, UVM/OVM, and coverage-based verification.
  • At least 3 years of experience in SystemVerilog, C/C++, and scripting languages such as Python, Ruby, or Perl.
  • Demonstrated experience with one or more of coherency, caches, fabrics, DDR controllers, PCIe, CXL, AXI/CHI protocol bridges, or other complex IP, blocks, or subsystems.
  • Experience with a full product cycle from definition to silicon, including writing IP/block or subsystem test plans, developing tests, debugging failures, and coverage signoff.
  • Experience creating, maintaining, or integrating test benches, checkers, and stimulus using SVTB, UVM, Formal Verification, and/or C/C++.
  • Experience automating verification processes using Python or another scripting language.

Responsibilities

  • Establish as an integral member of a pre-silicon verification and post-silicon validation team for custom silicon component development.
  • Write constrained-random stimulus, scoreboards, checkers, and assertions to verify design correctness.
  • Develop Verification IP (VIP) components for internally developed designs.
  • Develop Universal Verification Methodology (UVM) components that interface test code with verification simulation environments.
  • Define and implement functional coverage and drive coverage closure.
  • Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management, and third-party vendor teams to ensure comprehensive pre- and post-silicon testing.
  • Develop scripts for verification and validation infrastructure.
  • Embody Microsoft's Culture and Values.
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