Engineer Jobs

About The Position

Requirements

• At least 10 years of systems architecture experience in AI, HPC, or hyperscale compute.
• Experience taking at least one platform from paper to production at cluster scale.
• Deep understanding of scale-up versus scale-out architecture and the ability to explain and quantify tradeoffs between large NVLink domains and tuned RDMA fabrics.
• Hands-on experience with NVLink/NVSwitch, InfiniBand, and RoCEv2, including PFC, ECN, and DCQCN; familiarity with UALink and Ultra Ethernet.
• Fluency in GPU architecture, including SM and tensor-core design, HBM capacity and bandwidth, low-precision formats such as FP8 and FP4/MXFP4, and their implications for prefill and decode.
• Knowledge of Arm and x86 server architectures, including Grace, Neoverse, EPYC, and Xeon; NUMA; PCIe Gen5/Gen6; CXL; and host roles in data movement and KV-cache tiering.
• Working knowledge of modern inference software and serving concepts, including disaggregated serving, continuous batching, paged attention, KV-cache reuse and transfer, and MoE parallelism.
• Hands-on experience with at least one of SGLang, vLLM, TensorRT-LLM, or NVIDIA Dynamo.
• Ability to build performance and TCO models from first principles and defend them with benchmarks.
• Active involvement in the AI/HPC ecosystem through papers, open-source projects, OCP or MLPerf work, conference talks, or deep vendor relationships.
• Comfort owning ambiguous, cross-disciplinary problems at an early-stage company and working directly in a cluster when needed.

Nice To Haves

• Silicon or microarchitecture background in CPU, GPU, NPU, or network ASIC design or performance architecture.
• Experience with rack-scale systems, liquid cooling, busbar or DC power distribution, or 800G/1.6T optics.
• Familiarity with power electronics, DC-coupled architectures, or behind-the-meter power.
• Collective-communication experience with NCCL, RCCL, NVSHMEM, or NIXL, or HPC experience with MPI-scale jobs.
• Contributions to SGLang, vLLM, Dynamo, LMCache, or similar serving projects.
• Experience evaluating non-GPU inference accelerators and developing the business case for or against them.
• Published papers or patents in computer architecture, networking, or ML systems.

Responsibilities

• Define the next-generation RELIC compute platform and evaluate accelerators, host CPUs, NICs, and DPUs across NVIDIA, AMD, and emerging inference silicon.
• Choose between HGX-class nodes and rack-scale NVL systems for each site.
• Architect scale-up domains, including NVLink/NVSwitch sizing and partitioning, and assess alternatives such as UALink and Ethernet-based scale-up.
• Determine the scale-up domain size appropriate for each workload.
• Architect scale-out and front-end fabrics, including topology, RoCEv2 congestion control, Ultra Ethernet readiness, optics and transceiver strategy, and storage and KV-cache networks.
• Co-design the inference stack with the hardware by mapping serving approaches and parallelism strategies onto the platform.
• Work hands-on with SGLang, vLLM, TensorRT-LLM, and NVIDIA Dynamo.
• Build and maintain performance, roofline, and TCO models covering throughput, latency SLOs, performance per watt, cost per token, and tokens per second per megawatt; validate models against cluster measurements.
• Own the roadmap and technical relationships with NVIDIA, AMD, OEMs, and network vendors; lead technical deep-dives and influence early-access programs.
• Write architecture specifications for procurement and site teams.
• Lead bring-up and validation of new platforms and drive root-cause analysis of fabric-, NIC-, and node-level issues that block production.