Director Of Engineering Jobs

About The Position

Requirements

• Bachelor’s degree in Electrical Engineering or a related technical field.
• 12–15+ years of relevant experience, consistent with Astera Labs’ standardized Director level.
• Technical management experience leading design, validation, product, or system engineering teams.
• Experience with high-speed SerDes PHY validation over PVT conditions and taking products from concept through validation planning, validation, production release, and post-production support.
• Strong background in high-speed SerDes IP validation and PHY tuning, signal and power integrity, and automation using common lab equipment such as high-speed oscilloscopes, BERTs, and VNAs.
• Entrepreneurial, open-minded, can-do attitude, and customer-oriented approach.
• Strong cross-functional collaboration, technical communication, prioritization, and independent problem-solving skills.

Nice To Haves

• Master’s degree in Electrical Engineering.
• Experience leading SoC debug and development for high-speed interfaces such as PCIe 5, PCIe 6, or PAM4 802.3 Ethernet.
• Working knowledge of high-speed PHY design blocks such as PLLs, DFE, Tx EQ, FFE, and CDR, as well as signaling concepts such as PAM4.
• Strong Python scripting ability, knowledge of object-oriented programming, and basic DevOps using Git for source control and collaboration.
• Deep background developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.
• Proficiency using high-speed laboratory equipment such as BERTs, oscilloscopes, and VNAs.
• Startup experience and a proactive, hands-on, customer-focused approach to solving complex problems.

Responsibilities

• Lead ASIC electrical-level (PHY) validation strategy across product definition, architecture, PCB and test-fixture development, validation automation, data review, bring-up, debug, optimization, qualification, and production release.
• Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP.
• Make hands-on technical contributions to resolve critical design, validation, and customer issues.
• Direct ASIC power-on and bring-up, silicon and PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions.
• Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above.
• Apply signal and power integrity, SerDes/PHY knowledge, coding, and laboratory expertise to identify risks and develop solutions involving circuits, power distribution, connectors, sockets, and cables.
• Partner with ASIC, system validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams to deliver robust products.
• Engage internal customers to understand system requirements, evaluate form factors, propose complete board solutions, and resolve issues through production support.
• Collaborate with external vendors for test equipment, bench sockets, temperature forcing units, RF cables, PCB vendors, and related suppliers to ensure validation platforms are automated, robust, and scalable.
• Build, mentor, and develop a high-performing engineering team, establishing clear ownership, technical standards, and execution mechanisms.
• Drive products from concept to mass production, including validation data reviews, code and automation reviews, validation reporting, documentation, and post-production support.
• Improve post-silicon development processes and methodologies, share lessons learned, and reuse validation best practices across Astera Labs’ connectivity and memory product portfolio.

Benefits

• The role may be eligible for discretionary bonus, incentives, and benefits.