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Staff Logic Design Engineer

Teledyne Technologies Incorporated•Milpitas, CA
•$141,900 - $189,200•Onsite

About The Position

Teledyne LeCroy is seeking a Staff Logic Design Engineer to join its high-speed Protocol Team, which develops test and measurement products for high-speed serial data communications. The role involves architecting and implementing high-performance digital logic for protocol capture, analysis, and emulation in FPGA-based systems that decode and analyze high-speed protocols in real time. The engineer will collaborate with cross-functional teams to develop and validate protocol analyzer platforms.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
  • At least 7 years of experience in digital logic design for FPGA or ASIC.
  • Strong proficiency in Verilog/SystemVerilog RTL design.
  • Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, or SATA.
  • Experience with monitoring and/or test and measurement tools.
  • Experience with PCIe Gen4, Gen5, or Gen6 and familiarity with TLP, DLLP, and PHY-layer concepts.
  • Hands-on experience with FPGA toolchains such as Vivado or Quartus and with timing closure.
  • Knowledge of UVM, assertions, and simulation/debug tools such as ModelSim or Vivado Simulator.
  • Solid understanding of clock-domain crossing (CDC), clock-domain design, and reset strategies.

Nice To Haves

  • Master’s degree in Electrical Engineering.
  • Experience with protocol analyzers, packet capture, and timestamping logic.
  • Familiarity with AXI interconnects, memory controllers, and high-speed buffering.
  • Exposure to SERDES, PCIe IP integration, and link training/debug.
  • Scripting experience with Python or Tcl for automation and test infrastructure.
  • Experience with hardware/software co-design, register maps, and embedded firmware interaction.
  • Prior experience in test and measurement or semiconductor validation environments.

Responsibilities

  • Develop synthesizable Verilog/SystemVerilog RTL for high-speed protocol processing, packet parsing, timestamping, and buffer management.
  • Design high-throughput datapaths and control logic optimized for latency, bandwidth, and resource efficiency.
  • Develop FPGA solutions targeting Xilinx Versal and Intel Agilex devices, including synthesis, place and route, timing closure, and resource optimization.
  • Integrate PCIe IP cores, DMA engines, and custom protocol decoders.
  • Build SystemVerilog/UVM testbenches for block- and system-level verification.
  • Conduct simulation, waveform analysis, and functional coverage to ensure robust designs.
  • Collaborate with hardware, firmware, and software teams to bring up and validate protocol analyzer platforms.
  • Support laboratory debugging using logic analyzers, oscilloscopes, and in-system FPGA tools such as ILA and SignalTap.
  • Create design specifications, interface documents, and verification plans.
  • Participate in design and code reviews and contribute to continuous improvement of design practices.

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