Physical Design Clocking Engineer

Intel Corporation•Santa Clara, CA

6d•$105,650 - $149,150•Hybrid

About The Position

As a Physical Design Engineer in Intel's Data Center Group (DCG), you will implement custom IP and SoC designs by transforming RTL to GDS and producing design databases ready for manufacturing. You will execute physical design activities including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis. The work contributes to optimizing power, frequency, and area for Intel products. DCG develops technologies for data centers, cloud services, and high-performance computing environments. This role is part of a collaborative team focused on technical excellence and innovation. You will also contribute to physical design methodologies, flows, and automation processes, using industry-standard EDA tools. The position is based in Santa Clara, California, and is eligible for Intel's hybrid work model, which splits time between the assigned Intel site and off-site work. The listed annual salary range for US locations is $105,650 to $149,150; compensation within the range depends on work location and job-related skills, experience, and education or training.

Requirements

Bachelor's degree in a relevant field and 0–1 years of hands-on physical design experience, with skills gained through internships, academic projects, coursework, or hands-on training; alternatively, a Master's degree in a relevant field with no prior professional experience.
Proficiency with physical design tools, such as synthesis, place-and-route, and timing analysis software.
Familiarity with EDA tools and methodologies used in physical design and verification workflows.

Nice To Haves

Strong analytical and problem-solving skills to identify and resolve design violations.
Excellent communication and collaboration abilities for contributing in a dynamic team environment.
A proactive mindset and eagerness to learn and improve physical design methodologies and flows.

Responsibilities

Conduct physical design implementation, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
Perform verification and signoff activities, including equivalence verification, reliability verification, layout verification, and structural design checking.
Analyze results and recommend ways to resolve violations in current and future architectures.
Optimize designs to improve product-level power, frequency, and area.
Help develop and enhance physical design methodologies, flows, and automation processes.
Use industry-standard EDA tools to execute and validate physical design processes.