Distinguished Engineer, SerDes Clocking

Upscale, Inc. • Headquarters, KY

13d • $313,000 - $353,000

About The Position

Upscale, Inc. is seeking a senior individual contributor and technical leader to define the clocking architecture for next-generation SerDes, including ultra-low-jitter phase-locked loops (PLLs) and high-performance clock distribution networks. The role will establish clocking architecture and design methodology for the next-generation SerDes platform, addressing jitter, coupling, and power-efficiency challenges in advanced CMOS technologies at 5nm and below.

The engineer will lead architectural innovation and critical circuit development while working across analog, mixed-signal, digital, layout, package, and system teams. The position includes developing and delivering clocking solutions that meet demanding timing and noise requirements for AI data centers and high-performance computing, and supporting design execution through silicon characterization and simulation-to-silicon correlation.

Requirements

• MS or PhD in Electrical Engineering or a related field.
• Extensive experience in high-performance analog and mixed-signal IC design.
• Demonstrated success designing and delivering ultra-low-jitter PLLs with 100 fs-class RMS integrated jitter in advanced CMOS technologies at 5nm or below.
• Deep expertise in PLL architecture and circuit design, including phase detectors or phase-frequency detectors, charge pumps where applicable, loop filters, oscillators, frequency dividers, and loop dynamics.
• Strong understanding of phase noise, integrated jitter, reference spurs, loop stability, supply-induced jitter, and the impact of clock quality on high-speed SerDes performance.
• Ability to define clocking architectures and translate system-level jitter requirements into circuit-level specifications and implementation strategies.
• Experience with clock distribution design and management of coupling, skew, power integrity, and electromagnetic interactions.
• Hands-on experience with electromagnetic simulation and extraction tools for high-frequency circuits and passive structures.
• Experience developing SystemVerilog-based behavioral models and verification environments for PLLs or other mixed-signal clocking systems.
• Strong track record of technical leadership, architectural decision-making, and successful silicon delivery.

Nice To Haves

• Direct experience developing clocking solutions for 100G+ per-lane SerDes.
• Experience with hybrid PLL architectures, digital PLLs, digitally assisted analog PLLs, or other advanced clock-generation techniques.
• Expertise in resonant clock distribution, including resonant network design, energy recovery, clock power optimization, and implementation trade-offs.
• Experience managing interference among multiple high-performance PLLs on a shared die, including reference distribution, supply isolation, substrate coupling, and electromagnetic coupling.
• Proficiency with Cadence EMX, Ansys HFSS, or equivalent electromagnetic solvers.
• Experience with advanced-node physical implementation, custom layout, parasitic extraction, and silicon debug.
• Recognized technical contributions through successful silicon products, patents, publications, or industry-leading clocking innovations.

Responsibilities

• Define and drive the end-to-end clocking architecture for next-generation SerDes, including PLLs, clock generation, multiphase clocking, clock distribution, and integration with transmitter and receiver subsystems.
• Lead the architecture and development of ultra-low-jitter PLLs targeting less than 100 fs RMS integrated jitter in advanced CMOS at 5nm and below.
• Evaluate and develop hybrid, digital, and other advanced PLL architectures, balancing jitter, power, area, tuning range, robustness, and implementation complexity.
• Develop architectural and circuit-level solutions to mitigate coupling among PLLs and clock-generation blocks, including supply coupling, substrate noise, electromagnetic interactions, reference spurs, and clock-to-clock interference.
• Define and implement clock distribution architectures, including resonant clocking techniques, to reduce power while meeting jitter, skew, phase-noise, and timing requirements.
• Use electromagnetic simulation and extraction tools to analyze and optimize inductors, resonant networks, clock distribution structures, coupling paths, and high-frequency interconnects.
• Develop SystemVerilog-based behavioral models, verification environments, and architectural models for PLLs and clocking subsystems to enable early system integration, design exploration, and verification.
• Partner with SerDes TX, RX, ADC, digital, AMS layout, package, and silicon validation teams to optimize link performance and align clocking decisions with system requirements.
• Drive design reviews, implementation strategy, silicon characterization, jitter and phase-noise analysis, and simulation-to-silicon correlation.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior