Physical Design Clocking Engineer

Intel•Santa Clara, CA

4d•Hybrid

About The Position

As a Physical Design Engineer, you will implement custom IP and SoC designs, transforming RTL to GDS and producing design databases ready for manufacturing. You will execute physical design activities including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis, contributing to the optimization of power, frequency, and area. The role is part of Intel's Data Center Group (DCG), which develops technologies for data centers, cloud services, and high-performance computing environments in a collaborative, technically focused environment.

Requirements

Bachelor's degree in a relevant field and 0–1 years of hands-on physical design experience, which may be gained through internships, academic projects, coursework, or hands-on training; OR a Master's degree in a relevant field with no prior professional experience.
Proficiency with physical design tools, such as synthesis, place-and-route, and timing-analysis software.
Familiarity with EDA tools and methodologies used in physical design and verification workflows.

Nice To Haves

Strong analytical and problem-solving skills to identify and resolve design violations.
Excellent communication and collaboration abilities.
A proactive mindset and eagerness to learn and improve physical design methodologies and flows.

Responsibilities

Conduct physical design implementation tasks, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
Perform verification and signoff activities, such as equivalence verification, reliability verification, layout verification, and structural design checking.
Analyze results and recommend solutions to resolve violations for current and future architectures.
Optimize designs to improve product-level power, frequency, and area.
Participate in developing and enhancing physical design methodologies, flows, and automation processes.
Use industry-standard EDA tools to execute and validate physical design processes.