ASIC Design Engineer - Cache Controller
Apple • Santa Clara, CA124d
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ASIC Design Engineer - Cache Controller
Apple•Santa Clara, CA
About The Position
Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy. Design and develop hardware for cache subsystem in high performance system on a chip (SoC). Develop cache micro-architecture based on architecture guidelines and model analysis. Explore architecture trade-offs in system performance, area, and power consumption. Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem. Work on front-end netlist and area/timing analysis of the cache subsystem. Work with physical design team on the timing closure of the cache subsystem.
Requirements
- 10 + years of full time ASIC design experience memory system development
- RTL/micro-architecture definition
- PPA (performance/power/area) analysis
- Cache design background including an understanding of different memory organizations and tradeoffs.
- Hands on Experience with multi-processor cache coherence protocols
- B.S. in a relevant field
Nice To Haves
- Knowledge of high-performance coherent memory systems or interconnect architectures
- Knowledge of high-performance DRAM controller
- M.S in a relevant field.
Responsibilities
- Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
- Develop cache micro-architecture based on architecture guidelines and model analysis.
- Explore architecture trade-offs in system performance, area, and power consumption.
- Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
- Work on front-end netlist and area/timing analysis of the cache subsystem.
- Work with physical design team on the timing closure of the cache subsystem.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
Job Search Resources
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