Physical Design Engineer Jobs

About The Position

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering, or a related field.
• Experience and/or education using place-and-route tools such as ICC, ICC2, or Innovus for floor planning, placement, clock optimization, routing, and timing and power optimization for SoC partitions.
• End-to-end understanding of digital design implementation fundamentals, logic modeling, and hardware description languages used in digital IC design.
• Experience using TCL, Perl, Python, and Unix scripting to summarize data, improve execution efficiency, and implement custom scripts that aid partition closure.
• Understanding of physical-design construction and analysis flows and methodologies to execute, close, and sign off SoC partitions.
• Understanding of transistors and digital circuits to make implementation, closure, and signoff trade-offs that meet requirements.
• Understanding of digital logic and computer-architecture fundamentals relevant to IC partitioning and resource planning.
• Ability to interpret results from physical-verification tools such as Calibre and generate fixes for violations.
• Knowledge of signal behavior, interference effects, and noise-reduction principles relevant to high-speed digital circuits.

Responsibilities

• Work with logic design teams to understand partition architecture and address physical-design considerations early in the design cycle.
• Complete netlist-to-GDS2 implementation for partitions while meeting schedule and design goals.
• Own timing, physical and electrical verification, and signoff closure for partitions.
• Resolve physical-design and flow issues, identify potential solutions, and drive their execution.
• Coordinate place-and-route work, set goals and milestones, plan short- and long-term work, and manage dependencies across top-level design, STA, and block place-and-route domains.
• Advance physical-design methodologies and best-known methods; develop guidelines and checklists, drive execution, and track progress.
• Drive timing closure through physical synthesis and place-and-route tools, working with ASIC vendors.
• Drive frontend and backend implementation from RTL to GDS2, including synthesis, FV, floor planning, netlisting, timing constraints, timing and power convergence, and ECO implementation.
• Perform hands-on physical implementation and timing closure for core platforms and SoCs.
• Improve timing signoff criteria, timing-analysis methodologies and flows, and ECO-generation scripts for timing closure.
• Perform floor planning, physical synthesis, and physical-design closure for large complex designs with clock cycles above 1 GHz.
• Drive physical-design and timing convergence for high-frequency, low-power designs at block, cluster, and/or full-chip level.

Benefits

• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to advancing a career at Apple.
• Potential eligibility for discretionary bonuses or commission payments.
• Potential relocation assistance.
• Opportunity to participate in discretionary restricted stock unit awards.
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan, subject to eligibility and plan terms.