Sr. ASIC Physical Design Engineer

Hewlett Packard Enterprise • Sunnyvale, CA

2d • Hybrid

About The Position

As a block-level Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:

Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing.
Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub - chips at a large SoC level.
Collaborate with the packaging team on Microbump / Probe Bump/ Bump/Pad placement.
Build block level floorplan, including block pins, macro placement and alignment, power grid , etc.
Develop the block-level clock network and clock structure in collaboration with clock experts.
generating block/chip-level static timing constraints.
Arrange, analyze, and optimize feedthrough and repeaters among all blocks
Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.
Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.
Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.
Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.
Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts .

Requirements

• BS degree in electrical engineering, computer engineering, or a related field with 3+ years of experience in block or full-chip physical design, or MS degree in the above fields with 2+ years of related experience.
• Deep design experience in large SoC designs, including IP integration.
• Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.
• Experience in implementing power-grid and clock network at block level.
• Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.
• Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.
• Experience in custom place and route.
• Proficiency in writing Linux shell scripts in Perl, TCL, and Python.
• Real chip tapeout experience in 7nm and/or below with a successful signoff track record .
• Self-motivated with strong problem-solving and debugging skills.
• Ability to work effectively in a dynamic group environment.

Nice To Haves

• Exposure to 2.5D/3D packaging is preferred.
• High performance and large chip design experience is preferred.
• Exposure to DFT is preferred.

Responsibilities

• Implement physical design at the large SoC block level from RTL to GDSII, creating a design database ready for manufacturing.
• Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub - chips at a large SoC level.
• Collaborate with the packaging team on Microbump / Probe Bump/ Bump/Pad placement.
• Build block level floorplan, including block pins, macro placement and alignment, power grid , etc.
• Develop the block-level clock network and clock structure in collaboration with clock experts.
• generating block/chip-level static timing constraints.
• Arrange, analyze, and optimize feedthrough and repeaters among all blocks
• Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.
• Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.
• Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.
• Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.
• Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts .

Benefits

• Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior