SR ASIC Design Verification Engineer
About The Position
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Participate in the ASIC design verification for Cisco high-end switching products. Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis. Construct testbenches components like scoreboard, agents, sequencers, and monitors. Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration Ensure comprehensive verification coverage through code and functional coverage implementation and review
Requirements
- Bachelor's degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master's in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience.
- Prior experience in System Verilog and UVM.
- Experience with ASIC design and verification processes, debugging, methodology, and tools.
- Experience in verifying blocks/clusters or full chip level for ASIC.
Nice To Haves
- Post-silicon lab bring-up experience.
- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS
- Experience with Linux, C/C++, and/or Python/Perl.
- Experience in Networking.
Responsibilities
- Participate in the ASIC design verification for Cisco high-end switching products.
- Architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure
- Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.
- Construct testbenches components like scoreboard, agents, sequencers, and monitors.
- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration
- Ensure comprehensive verification coverage through code and functional coverage implementation and review
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- paid holidays
- floating holiday
- paid time off for employee’s birthday
- paid year-end holiday shutdown
- paid days off for personal wellness
- paid vacation time
- sick time off
- paid days per full calendar year to volunteer
- annual bonuses
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What This Job Offers
Job Type
Full-time
Career Level
Senior
Number of Employees
5,001-10,000 employees
