Sr. ASIC Design Engineer

Hewlett Packard Enterprise•Roseville, CA

3d•Onsite

About The Position

HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.

Requirements

Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 5+ years of relevant experience.
Strong analytical/problem solving skills.
Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus.
Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired.
Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired.
Excellent written and verbal communications skills are good to have.
Knowledge of Perl/Python is a plus.
Experience with AI agentic tools is a plus.

Responsibilities

You will start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements.
You will implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs.
You will work with the Physical Design team for optimal floorplan and timing closure.
You will identify and fix timing in RTL to meet the frequency target.
Work with the Verification team to make sure your block is fully validated.
You will have opportunities to improve leadership skills by providing mentoring/guidance to new college-grad engineers and interns.