ASIC Design Engineer

Qualcomm • Santa Clara, CA

1d • $126,700 - $190,100 • Onsite

About The Position

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team you will be working with WiFi (802.11x) technology, SOC infrastructure, chip level verification and employ best-in-class Design and verification methodology.

Requirements

• 5+ years of industry experience in ASIC design, micro‑architecture, and design integration.
• Strong background in SoC micro‑architecture, including specification, definition, and implementation of functional blocks.
• Hands‑on experience with multi‑domain clocking implementation in SOCs including understanding of clocking architectures, clock/power domain partitioning.
• Experience in Design linting and CDC analysis, including triage and closure of violations.
• Solid understanding of AMBA bus protocols, including AHB and APB.
• Proficiency in Python/Perl is required.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field.

Nice To Haves

• Exposure to AI/ML based design methodologies is a strong plus
• Experience with ARM CoreSight architecture and debug interfaces.
• Experience with AXI Bus protocol
• Experience with PCIe and/or USB peripheral subsystems
• Low Power design and implementation
• Chip interconnect (NOC) implementation

Responsibilities

• Micro-architecture, RTL design, and development of new functional blocks, as well as subsystem and full‑chip integration.
• Ownership of the design through the complete ASIC lifecycle, from concept through tape‑out.
• Collaboration with other subsystem teams to ensure smooth integration of releases.
• Interfacing with verification, DFT, FPGA emulation, and implementation teams.

Benefits

• Competitive annual discretionary bonus program
• Opportunity for annual RSU grants
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level