ASIC Design Verification Engineer

Qualcomm•Markham, ON

About The Position

Qualcomm-Atheros is a leading provider of wireless and wired technologies for the mobile, networking, computing and consumer electronics markets. We're focused on inventing technologies that connect and empower people in ways that are elegant and accessible to all. Qualcomm Atheros' teams deliver cutting-edge products across every established wireless standard/protocol. We are currently seeking candidates for positions involving the implementation of optimum system architectures, interfaces and logics for connectivity RF/Analog system. Successful candidates will be responsible for participating in development of leading-edge ASICs for multi-function mobile platforms. Candidates will work with engineers or develop unit-level and integrated-level test benches. Candidate will assist in synthesis and gate-level simulation tasks related to your module and will assist with timing of the entire chip. Candidate will leverage knowledge of wireless LAN, Bluetooth, and RF transceiver.

Requirements

RTL Design
ASIC front-end experience
Scripting Languages knowledge (e.g. Perl or Python)
Strong understanding of RF-analog and digital logic design.
Proficient in SystemVerilog, Python, Perl, C-Shell, and Cadence SKILL.
Experience with Cadence AMS/XCelium tools.
Familiarity with serial bus interfaces, register controllers, and state machines.
Knowledge of RF transceiver architectures, PLLs, ADCs, DACs.
Experience with UVM and functional verification of RF/mixed-signal chips.
AI/ML Fundamentals: Understanding of supervised/unsupervised learning, neural networks, and ML-based optimization.
Experience with ML libraries such as TensorFlow, PyTorch, Scikit-learn, and EDA-specific ML tools.
Ability to tailor ML models to analog/RF design topologies and verification tasks.
Experience with Prompt Engineering for AI/ML model interaction and optimization.
Bachelor's degree in Science, Engineering, or related field.

Responsibilities

Develop and debug behavioral models for event-driven and mixed-signal simulation based on analog circuit design.
Create verification plans for radio and IP modules interfacing with SoC.
Build self-checking test benches and define test coverages and sequences.
Maintain scripts for netlist release and programming instruction generation.
Diagnose failed tests and manage bug tracking and resolution.
Contribute to methodology development, especially in AI/ML-enhanced verification flows.
Apply ML models to predict boundary values and optimize test coverage early in the design cycle.